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5392ad2fd9
Explicitly flush icache on the CR52 core before jumping to the next stage software to make sure it does not contain any invalid content. Explicitly flash and invalidate dcache on the CA76 core both over the trampoline buffer and over the CR52 firmware, and then trigger full system synchronization, to make sure the data surely land in DRAM, from where the CR52 can surely pick them up. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
100 lines
3.5 KiB
C
100 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Specialty padding for the R-Car Gen2 SPL JTAG loading
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*/
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#ifndef __BOOT0_H
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#define __BOOT0_H
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#if IS_ENABLED(CONFIG_RCAR_GEN2)
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_start:
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ARM_VECTORS
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#ifdef CONFIG_XPL_BUILD
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.word 0x0badc0d3;
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.word 0x0badc0d3;
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.word 0x0badc0d3;
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.word 0x0badc0d3;
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.word 0x0badc0d3;
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.word 0x0badc0d3;
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.word 0x0badc0d3;
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.word 0x0badc0d3;
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#endif
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#endif
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#if IS_ENABLED(CONFIG_R8A779G0)
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#ifdef CONFIG_XPL_BUILD
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/* r1=0xe6170800 */
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.inst 0xe3a004e6 /* mov r0, #0xe6000000 */
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.inst 0xe3801817 /* orr r1, r0, #0x170000 */
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.inst 0xe3814b02 /* orr r4, r1, #0x800 */
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/* r0=0xe6280000 */
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.inst 0xe380070a /* orr r0, r0, #0x280000 */
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/* APMU_RVBARPLC0 = (address of 'b reset' below) | CA_CORE0_VLD_RVBARP */
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.inst 0xe28f30a8 /* add r3, pc, #0xa8 */
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.inst 0xe3833001 /* orr r3, r3, #1 */
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.inst 0xe5843038 /* str r3, [r4, #56] @ 0x38 */
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/* APMU_RVBARPHC0 = 0 */
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.inst 0xe3a05000 /* mov r5, #0 */
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.inst 0xe584503c /* str r5, [r4, #60] @ 0x3c */
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/* PRR & 0xff00 ?= 0x5c00, test if this is V4H or V4M */
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.inst 0xe3a024ff /* mov r2, #0xff000000 */
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.inst 0xe382260f /* orr r2, r2, #0xf00000 */
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.inst 0xe5923044 /* ldr r3, [r2, #68] @ 0x44 */
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.inst 0xe2033cff /* and r3, r3, #0xff00 */
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.inst 0xe3530b17 /* cmp r3, #0x5c00 */
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.inst 0x1a00000a /* bne 68 <reset-0x18> */
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/* if (SoC is V4H) { */
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/* AP_CORE_APSREG_AP_CLUSTER_N_AUX0 |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT */
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.inst 0xe5903010 /* ldr r3, [r0, #16] */
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.inst 0xe3833003 /* orr r3, r3, #3 */
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.inst 0xe5803010 /* str r3, [r0, #16] */
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/* AP_CORE_APSREG_CCI500_AUX |= AP_CORE_APSREG_CCI500_AUX_ACTDIS */
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.inst 0xe3800a09 /* orr r0, r0, #36864 @ 0x9000 */
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.inst 0xe5903010 /* ldr r3, [r0, #16] */
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.inst 0xe3833001 /* orr r3, r3, #1 */
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.inst 0xe5803010 /* str r3, [r0, #16] */
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/* AP_CORE_APSREG_P_CCI500_AUX |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM */
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.inst 0xe3800802 /* orr r0, r0, #131072 @ 0x20000 */
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.inst 0xe5903010 /* ldr r3, [r0, #16] */
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.inst 0xe3833002 /* orr r3, r3, #2 */
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.inst 0xe5803010 /* str r3, [r0, #16] */
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/* } */
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/* APMU_PWRCTRLC0 = CA_CORE0_WUP_REQ */
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.inst 0xe3a03001 /* mov r3, #1 */
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.inst 0xe5843000 /* str r3, [r4] */
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/* Test for APMU_CRBARP valid BAR flags and jump to CR entry point */
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.inst 0xe3814c03 /* orr r4, r1, #768 @ 0x300 */
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.inst 0xe584503c /* str r5, [r4, #60] @ 0x3c */
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.inst 0xe594203c /* ldr r2, [r4, #60] @ 0x3c */
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.inst 0xe20230ff /* and r3, r2, #255 @ 0xff */
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.inst 0xe3530011 /* cmp r3, #17 */
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.inst 0x1afffffb /* bne 78 <reset-0x28> */
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/* Invalidate icache before jump to follow up software */
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.inst 0xe3a00000 /* mov r0, #0 */
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.inst 0xee070f15 /* mcr 15, 0, r0, cr7, cr5, {0} */
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.inst 0xf57ff04f /* dsb sy */
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.inst 0xf57ff06f /* isb sy */
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/* Jump to follow up software */
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.inst 0xe1a02922 /* lsr r2, r2, #18 */
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.inst 0xe1a02902 /* lsl r2, r2, #18 */
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.inst 0xe1a0f002 /* mov pc, r2 */
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.inst 0xeafffffe /* b 94 <reset-0xc> */
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.inst 0xe1a00000 /* nop @ (mov r0, r0) */
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.inst 0xe1a00000 /* nop @ (mov r0, r0) */
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.inst 0xe1a00000 /* nop @ (mov r0, r0) */
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.inst 0xe1a00000 /* nop @ (mov r0, r0) */
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.inst 0xe1a00000 /* nop @ (mov r0, r0) */
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.inst 0xe1a00000 /* nop @ (mov r0, r0) */
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/* Offset 0xa0 */
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#endif
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b reset
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#endif
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#endif /* __BOOT0_H */
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