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69a5616f06
These header files presumably duplicate things already in the U-Boot devicetree. For now, bring them in to get the ASL code and ACPI table code to compile. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Matthias Brugger <mbrugger@suse.com> Cc: Matthias Brugger <mbrugger@suse.com> Cc: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Rini <trini@konsulko.com>
153 lines
6.7 KiB
C
153 lines
6.7 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause-Patent */
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/**
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*
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* Copyright (c) 2019, Jeremy Linton
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* Copyright (c) 2019, Pete Batard <pete@akeo.ie>.
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*
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**/
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#ifndef BCM2711_H__
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#define BCM2711_H__
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#define BCM2711_SOC_REGISTERS 0xfc000000
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#define BCM2711_SOC_REGISTER_LENGTH 0x02000000
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#define BCM2711_ARM_LOCAL_REGISTERS 0xfe000000
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#define BCM2711_ARM_LOCAL_REGISTER_LENGTH 0x02000000
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/* arm local addresses */
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#define BCM2711_ARMC_OFFSET 0x0000b000
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#define BCM2711_ARMC_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARMC_OFFSET)
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#define BCM2711_ARMC_LENGTH 0x00000400
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#define BCM2711_ARM_LOCAL_OFFSET 0x01800000
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#define BCM2711_ARM_LOCAL_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARM_LOCAL_OFFSET)
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#define BCM2711_ARM_LOCAL_LENGTH 0x00000080
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#define BCM2711_GIC400_OFFSET 0x01840000
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#define BCM2711_GIC400_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_GIC400_OFFSET)
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#define BCM2711_GIC400_LENGTH 0x00008000
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/* Generic PCI addresses */
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#define PCIE_TOP_OF_MEM_WIN 0xf8000000
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#define PCIE_CPU_MMIO_WINDOW 0x600000000
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#define PCIE_BRIDGE_MMIO_LEN 0x3ffffff
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/* PCI root bridge control registers location */
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#define PCIE_REG_BASE 0xfd500000
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#define PCIE_REG_LIMIT 0x9310
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/* PCI root bridge control registers */
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#define BRCM_PCIE_CAP_REGS 0x00ac
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#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
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#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
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#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
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#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
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#define LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
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#define PCIE_RC_DL_MDIO_ADDR 0x1100
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#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
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#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
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#define PCIE_MISC_MISC_CTRL 0x4008
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#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
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#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
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#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
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#define MISC_CTRL_MAX_BURST_SIZE_128 0x0
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#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
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#define PCIE_MEM_WIN0_LO(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
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#define PCIE_MEM_WIN0_HI(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
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#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
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#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
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#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
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#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
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#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
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#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
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#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
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#define PCIE_MISC_PCIE_STATUS 0x4068
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#define STATUS_PCIE_PORT_MASK 0x80
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#define STATUS_PCIE_PORT_SHIFT 7
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#define STATUS_PCIE_DL_ACTIVE_MASK 0x20
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#define STATUS_PCIE_DL_ACTIVE_SHIFT 5
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#define STATUS_PCIE_PHYLINKUP_MASK 0x10
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#define STATUS_PCIE_PHYLINKUP_SHIFT 4
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#define PCIE_MISC_REVISION 0x406c
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
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#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
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#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
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#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
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#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
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#define MEM_WIN0_BASE_HI_BASE_MASK 0xff
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#define PCIE_MEM_WIN0_BASE_HI(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
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#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
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#define PCIE_MEM_WIN0_LIMIT_HI(win) \
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
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#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
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#define PCIE_INTR2_CPU_STATUS 0x4300
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#define PCIE_INTR2_CPU_SET 0x4304
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#define PCIE_INTR2_CPU_CLR 0x4308
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#define PCIE_INTR2_CPU_MASK_STATUS 0x430c
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#define PCIE_INTR2_CPU_MASK_SET 0x4310
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#define PCIE_INTR2_CPU_MASK_CLR 0x4314
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#define PCIE_MSI_INTR2_CLR 0x4508
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#define PCIE_MSI_INTR2_MASK_SET 0x4510
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#define PCIE_RGR1_SW_INIT_1 0x9210
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#define PCIE_EXT_CFG_INDEX 0x9000
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/* A small window pointing at the ECAM of the device selected by CFG_INDEX */
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#define PCIE_EXT_CFG_DATA 0x8000
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#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
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#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
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#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
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#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
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#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
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#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
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#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
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#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
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#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
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#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2
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#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
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#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_MASK_BITS 0xc
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#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
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#define BURST_SIZE_128 0
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#define BURST_SIZE_256 1
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#define BURST_SIZE_512 2
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#define BCM2711_THERM_SENSOR_OFFSET 0x015d2200
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#define BCM2711_THERM_SENSOR_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_THERM_SENSOR_OFFSET)
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#define BCM2711_THERM_SENSOR_LENGTH 0x00000008
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#define BCM2711_GENET_BASE_OFFSET 0x01580000
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#define BCM2711_GENET_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_GENET_BASE_OFFSET)
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#define BCM2711_GENET_LENGTH 0x10000
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#endif /* BCM2711_H__ */
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