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				https://source.denx.de/u-boot/u-boot.git
				synced 2025-10-31 00:11:51 +01:00 
			
		
		
		
	Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
		
			
				
	
	
		
			80 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			80 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
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|  *
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|  * Watchdog driver for Atmel AT91SAM9x processors.
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|  *
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|  * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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|  * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License
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|  * as published by the Free Software Foundation; either version
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|  * 2 of the License, or (at your option) any later version.
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|  */
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| 
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| /*
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|  * The Watchdog Timer Mode Register can be only written to once. If the
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|  * timeout need to be set from U-Boot, be sure that the bootstrap doesn't
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|  * write to this register. Inform Linux to it too
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|  */
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| 
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| #include <common.h>
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| #include <watchdog.h>
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| #include <asm/arch/hardware.h>
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| #include <asm/arch/io.h>
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| #include <asm/arch/at91_wdt.h>
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| 
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| /*
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|  * AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
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|  * use this to convert a watchdog
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|  * value from/to milliseconds.
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|  */
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| #define ms_to_ticks(t)	(((t << 8) / 1000) - 1)
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| #define ticks_to_ms(t)	(((t + 1) * 1000) >> 8)
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| 
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| /* Hardware timeout in seconds */
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| #define WDT_HW_TIMEOUT 2
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| 
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| /*
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|  * Set the watchdog time interval in 1/256Hz (write-once)
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|  * Counter is 12 bit.
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|  */
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| static int at91_wdt_settimeout(unsigned int timeout)
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| {
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| 	unsigned int reg;
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| 	unsigned int mr;
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| 
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| 	/* Check if disabled */
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| 	mr = at91_sys_read(AT91_WDT_MR);
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| 	if (mr & AT91_WDT_WDDIS) {
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| 		printf("sorry, watchdog is disabled\n");
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| 		return -1;
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| 	}
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| 
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| 	/*
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| 	 * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
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| 	 *
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| 	 * Since WDV is a 12-bit counter, the maximum period is
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| 	 * 4096 / 256 = 16 seconds.
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| 	 */
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| 	reg = AT91_WDT_WDRSTEN	/* causes watchdog reset */
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| 		/* | AT91_WDT_WDRPROC	causes processor reset only */
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| 		| AT91_WDT_WDDBGHLT		/* disabled in debug mode */
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| 		| AT91_WDT_WDD			/* restart at any time */
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| 		| (timeout & AT91_WDT_WDV);	/* timer value */
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| 	at91_sys_write(AT91_WDT_MR, reg);
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| 
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| 	return 0;
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| }
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| 
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| void hw_watchdog_reset(void)
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| {
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| 	at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
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| }
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| 
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| void hw_watchdog_init(void)
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| {
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| 	/* 16 seconds timer, resets enabled */
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| 	at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
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| }
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