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	The U-Boot port for ST-Ericsson Ux500 is currently only used on the "stemmy" board, where U-Boot runs after firmware that already sets up a boot splash screen. This means that the display is already on and we can just continue using it for U-Boot. Add a simple driver that simplifies this by reading the display configuration (e.g. screen size, bpp) from the hardware registers. It also checks the configured "source synchronization" - for some displays (usually DSI command mode displays) we need to explicitly trigger a software sync. This is done through the video_sync() callback that triggers the sync and wait for completion. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
		
			
				
	
	
		
			142 lines
		
	
	
		
			3.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			142 lines
		
	
	
		
			3.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /* Copyright (C) 2019 Stephan Gerhold */
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| 
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| #include <common.h>
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| #include <dm.h>
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| #include <log.h>
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| #include <video.h>
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| #include <asm/io.h>
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| #include <linux/bitfield.h>
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| #include <linux/iopoll.h>
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| 
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| #define MCDE_EXTSRC0A0			0x200
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| #define MCDE_EXTSRC0CONF		0x20C
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| #define MCDE_EXTSRC0CONF_BPP		GENMASK(11, 8)
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| #define MCDE_OVL0CONF			0x404
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| #define MCDE_OVL0CONF_PPL		GENMASK(10, 0)
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| #define MCDE_OVL0CONF_LPF		GENMASK(26, 16)
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| #define MCDE_CHNL0SYNCHMOD		0x608
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| #define MCDE_CHNL0SYNCHMOD_SRC_SYNCH	GENMASK(1, 0)
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| #define MCDE_CHNL0SYNCHSW		0x60C
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| #define MCDE_CHNL0SYNCHSW_SW_TRIG	BIT(0)
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| #define MCDE_CRA0			0x800
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| #define MCDE_CRA0_FLOEN			BIT(0)
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| 
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| #define MCDE_FLOW_COMPLETION_TIMEOUT	200000	/* us */
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| 
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| enum mcde_bpp {
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| 	MCDE_EXTSRC0CONF_BPP_1BPP_PAL,
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| 	MCDE_EXTSRC0CONF_BPP_2BPP_PAL,
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| 	MCDE_EXTSRC0CONF_BPP_4BPP_PAL,
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| 	MCDE_EXTSRC0CONF_BPP_8BPP_PAL,
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| 	MCDE_EXTSRC0CONF_BPP_RGB444,
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| 	MCDE_EXTSRC0CONF_BPP_ARGB4444,
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| 	MCDE_EXTSRC0CONF_BPP_IRGB1555,
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| 	MCDE_EXTSRC0CONF_BPP_RGB565,
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| 	MCDE_EXTSRC0CONF_BPP_RGB888,
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| 	MCDE_EXTSRC0CONF_BPP_XRGB8888,
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| 	MCDE_EXTSRC0CONF_BPP_ARGB8888,
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| 	MCDE_EXTSRC0CONF_BPP_YCBCR422,
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| };
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| 
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| enum mcde_src_synch {
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| 	MCDE_CHNL0SYNCHMOD_SRC_SYNCH_HARDWARE,
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| 	MCDE_CHNL0SYNCHMOD_SRC_SYNCH_NO_SYNCH,
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| 	MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SOFTWARE,
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| };
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| 
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| struct mcde_simple_priv {
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| 	fdt_addr_t base;
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| 	enum mcde_src_synch src_synch;
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| };
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| 
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| static int mcde_simple_probe(struct udevice *dev)
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| {
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| 	struct mcde_simple_priv *priv = dev_get_priv(dev);
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| 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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| 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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| 	u32 val;
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| 
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| 	priv->base = dev_read_addr(dev);
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| 	if (priv->base == FDT_ADDR_T_NONE)
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| 		return -EINVAL;
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| 
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| 	plat->base = readl(priv->base + MCDE_EXTSRC0A0);
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| 	if (!plat->base)
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| 		return -ENODEV;
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| 
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| 	val = readl(priv->base + MCDE_OVL0CONF);
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| 	uc_priv->xsize = FIELD_GET(MCDE_OVL0CONF_PPL, val);
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| 	uc_priv->ysize = FIELD_GET(MCDE_OVL0CONF_LPF, val);
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| 	uc_priv->rot = 0;
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| 
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| 	val = readl(priv->base + MCDE_EXTSRC0CONF);
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| 	switch (FIELD_GET(MCDE_EXTSRC0CONF_BPP, val)) {
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| 	case MCDE_EXTSRC0CONF_BPP_RGB565:
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| 		uc_priv->bpix = VIDEO_BPP16;
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| 		break;
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| 	case MCDE_EXTSRC0CONF_BPP_XRGB8888:
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| 	case MCDE_EXTSRC0CONF_BPP_ARGB8888:
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| 		uc_priv->bpix = VIDEO_BPP32;
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| 		break;
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| 	default:
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| 		printf("unsupported format: %#x\n", val);
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| 		return -EINVAL;
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| 	}
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| 
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| 	val = readl(priv->base + MCDE_CHNL0SYNCHMOD);
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| 	priv->src_synch = FIELD_GET(MCDE_CHNL0SYNCHMOD_SRC_SYNCH, val);
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| 
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| 	plat->size = uc_priv->xsize * uc_priv->ysize * VNBYTES(uc_priv->bpix);
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| 	debug("MCDE base: %#lx, xsize: %d, ysize: %d, bpp: %d\n",
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| 	      plat->base, uc_priv->xsize, uc_priv->ysize, VNBITS(uc_priv->bpix));
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| 
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| 	video_set_flush_dcache(dev, true);
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| 	return 0;
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| }
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| 
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| static int mcde_simple_video_sync(struct udevice *dev)
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| {
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| 	struct mcde_simple_priv *priv = dev_get_priv(dev);
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| 	unsigned int val;
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| 
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| 	if (priv->src_synch != MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SOFTWARE)
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| 		return 0;
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| 
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| 	/* Enable flow */
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| 	val = readl(priv->base + MCDE_CRA0);
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| 	val |= MCDE_CRA0_FLOEN;
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| 	writel(val, priv->base + MCDE_CRA0);
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| 
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| 	/* Trigger a software sync */
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| 	writel(MCDE_CHNL0SYNCHSW_SW_TRIG, priv->base + MCDE_CHNL0SYNCHSW);
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| 
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| 	/* Disable flow */
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| 	val = readl(priv->base + MCDE_CRA0);
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| 	val &= ~MCDE_CRA0_FLOEN;
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| 	writel(val, priv->base + MCDE_CRA0);
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| 
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| 	/* Wait for completion */
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| 	return readl_poll_timeout(priv->base + MCDE_CRA0, val,
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| 				  !(val & MCDE_CRA0_FLOEN),
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| 				  MCDE_FLOW_COMPLETION_TIMEOUT);
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| }
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| 
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| static struct video_ops mcde_simple_ops = {
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| 	.video_sync = mcde_simple_video_sync,
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| };
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| 
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| static const struct udevice_id mcde_simple_ids[] = {
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| 	{ .compatible = "ste,mcde" },
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| 	{ }
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| };
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| 
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| U_BOOT_DRIVER(mcde_simple) = {
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| 	.name		= "mcde_simple",
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| 	.id		= UCLASS_VIDEO,
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| 	.ops		= &mcde_simple_ops,
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| 	.of_match	= mcde_simple_ids,
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| 	.probe		= mcde_simple_probe,
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| 	.priv_auto	= sizeof(struct mcde_simple_priv),
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| };
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