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0205beb156
The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
69 lines
1.6 KiB
C
69 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 NXP
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*
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* PCIe DM U-Boot driver for Freescale PowerPC SoCs
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* Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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*/
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#ifndef _PCIE_FSL_H_
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#define _PCIE_FSL_H_
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/* GPEX CSR */
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#define CSR_CLASSCODE 0x474
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#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
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#define FSL_PCIE_CAP_ID 0x70
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#else
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#define FSL_PCIE_CAP_ID 0x4c
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#endif
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/* PCIe Device Control Register */
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#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08)
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/* PCIe Device Status Register */
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#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a)
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/* PCIe Link Control Register */
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#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10)
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/* PCIe Link Status Register */
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#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12)
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#define DBI_RO_WR_EN 0x8bc
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#ifndef CONFIG_SYS_PCI_MEMORY_BUS
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#define CONFIG_SYS_PCI_MEMORY_BUS 0
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#endif
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#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
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#define CONFIG_SYS_PCI_MEMORY_PHYS 0
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#endif
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#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
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#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024)
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#endif
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#define PEX_CSR0_LTSSM_MASK 0xFC
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#define PEX_CSR0_LTSSM_SHIFT 2
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#define LTSSM_L0_REV3 0x11
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#define LTSSM_L0 0x16
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struct fsl_pcie_data {
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u32 block_offset; /* Offset from CCSR of 1st controller */
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u32 block_offset_mask; /* Mask out the CCSR base */
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u32 stride; /* Offset stride between controllers */
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};
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struct fsl_pcie {
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int idx;
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struct udevice *bus;
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void __iomem *regs;
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u32 law_trgt_if; /* LAW target ID */
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u32 block_rev; /* IP block revision */
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bool mode; /* RC&EP mode flag */
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bool enabled; /* Enable status */
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struct list_head list;
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struct fsl_pcie_data *info;
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};
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extern struct list_head fsl_pcie_list;
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#endif /* _PCIE_FSL_H_ */
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