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45a1693a31
The device interface is 16 bits wide. All the available packets are read from the incoming fifo. Signed-off-by: Roberto Cerati <roberto.cerati@bticino.it> Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> [voice.shen@atmel.com: address comments from review results] [voice.shen@atmel.com: clean up for submit] Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
358 lines
9.5 KiB
C
358 lines
9.5 KiB
C
/*
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* drivers/net/ks8851_mll.c
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*
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* Supports:
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* KS8851 16bit MLL chip from Micrel Inc.
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*
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* Copyright (c) 2009 Micrel Inc.
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*
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* modified by
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* (c) 2011 Bticino s.p.a, Roberto Cerati <roberto.cerati@bticino.it>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _KS8851_MLL_H_
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#define _KS8851_MLL_H_
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#include <linux/types.h>
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#define KS_CCR 0x08
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#define CCR_EEPROM (1 << 9)
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#define CCR_SPI (1 << 8)
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#define CCR_8BIT (1 << 7)
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#define CCR_16BIT (1 << 6)
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#define CCR_32BIT (1 << 5)
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#define CCR_SHARED (1 << 4)
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#define CCR_32PIN (1 << 0)
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/* MAC address registers */
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#define KS_MARL 0x10
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#define KS_MARM 0x12
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#define KS_MARH 0x14
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#define KS_OBCR 0x20
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#define OBCR_ODS_16MA (1 << 6)
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#define KS_EEPCR 0x22
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#define EEPCR_EESA (1 << 4)
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#define EEPCR_EESB (1 << 3)
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#define EEPCR_EEDO (1 << 2)
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#define EEPCR_EESCK (1 << 1)
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#define EEPCR_EECS (1 << 0)
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#define KS_MBIR 0x24
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#define MBIR_TXMBF (1 << 12)
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#define MBIR_TXMBFA (1 << 11)
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#define MBIR_RXMBF (1 << 4)
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#define MBIR_RXMBFA (1 << 3)
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#define KS_GRR 0x26
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#define GRR_QMU (1 << 1)
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#define GRR_GSR (1 << 0)
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#define KS_WFCR 0x2A
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#define WFCR_MPRXE (1 << 7)
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#define WFCR_WF3E (1 << 3)
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#define WFCR_WF2E (1 << 2)
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#define WFCR_WF1E (1 << 1)
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#define WFCR_WF0E (1 << 0)
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#define KS_WF0CRC0 0x30
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#define KS_WF0CRC1 0x32
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#define KS_WF0BM0 0x34
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#define KS_WF0BM1 0x36
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#define KS_WF0BM2 0x38
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#define KS_WF0BM3 0x3A
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#define KS_WF1CRC0 0x40
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#define KS_WF1CRC1 0x42
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#define KS_WF1BM0 0x44
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#define KS_WF1BM1 0x46
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#define KS_WF1BM2 0x48
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#define KS_WF1BM3 0x4A
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#define KS_WF2CRC0 0x50
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#define KS_WF2CRC1 0x52
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#define KS_WF2BM0 0x54
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#define KS_WF2BM1 0x56
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#define KS_WF2BM2 0x58
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#define KS_WF2BM3 0x5A
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#define KS_WF3CRC0 0x60
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#define KS_WF3CRC1 0x62
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#define KS_WF3BM0 0x64
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#define KS_WF3BM1 0x66
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#define KS_WF3BM2 0x68
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#define KS_WF3BM3 0x6A
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#define KS_TXCR 0x70
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#define TXCR_TCGICMP (1 << 8)
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#define TXCR_TCGUDP (1 << 7)
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#define TXCR_TCGTCP (1 << 6)
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#define TXCR_TCGIP (1 << 5)
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#define TXCR_FTXQ (1 << 4)
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#define TXCR_TXFCE (1 << 3)
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#define TXCR_TXPE (1 << 2)
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#define TXCR_TXCRC (1 << 1)
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#define TXCR_TXE (1 << 0)
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#define KS_TXSR 0x72
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#define TXSR_TXLC (1 << 13)
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#define TXSR_TXMC (1 << 12)
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#define TXSR_TXFID_MASK (0x3f << 0)
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#define TXSR_TXFID_SHIFT (0)
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#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
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#define KS_RXCR1 0x74
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#define RXCR1_FRXQ (1 << 15)
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#define RXCR1_RXUDPFCC (1 << 14)
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#define RXCR1_RXTCPFCC (1 << 13)
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#define RXCR1_RXIPFCC (1 << 12)
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#define RXCR1_RXPAFMA (1 << 11)
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#define RXCR1_RXFCE (1 << 10)
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#define RXCR1_RXEFE (1 << 9)
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#define RXCR1_RXMAFMA (1 << 8)
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#define RXCR1_RXBE (1 << 7)
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#define RXCR1_RXME (1 << 6)
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#define RXCR1_RXUE (1 << 5)
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#define RXCR1_RXAE (1 << 4)
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#define RXCR1_RXINVF (1 << 1)
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#define RXCR1_RXE (1 << 0)
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#define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
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RXCR1_RXMAFMA | RXCR1_RXPAFMA)
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#define KS_RXCR2 0x76
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#define RXCR2_SRDBL_MASK (0x7 << 5)
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#define RXCR2_SRDBL_SHIFT (5)
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#define RXCR2_SRDBL_4B (0x0 << 5)
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#define RXCR2_SRDBL_8B (0x1 << 5)
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#define RXCR2_SRDBL_16B (0x2 << 5)
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#define RXCR2_SRDBL_32B (0x3 << 5)
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/* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
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#define RXCR2_IUFFP (1 << 4)
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#define RXCR2_RXIUFCEZ (1 << 3)
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#define RXCR2_UDPLFE (1 << 2)
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#define RXCR2_RXICMPFCC (1 << 1)
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#define RXCR2_RXSAF (1 << 0)
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#define KS_TXMIR 0x78
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#define KS_RXFHSR 0x7C
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#define RXFSHR_RXFV (1 << 15)
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#define RXFSHR_RXICMPFCS (1 << 13)
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#define RXFSHR_RXIPFCS (1 << 12)
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#define RXFSHR_RXTCPFCS (1 << 11)
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#define RXFSHR_RXUDPFCS (1 << 10)
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#define RXFSHR_RXBF (1 << 7)
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#define RXFSHR_RXMF (1 << 6)
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#define RXFSHR_RXUF (1 << 5)
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#define RXFSHR_RXMR (1 << 4)
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#define RXFSHR_RXFT (1 << 3)
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#define RXFSHR_RXFTL (1 << 2)
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#define RXFSHR_RXRF (1 << 1)
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#define RXFSHR_RXCE (1 << 0)
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#define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
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RXFSHR_RXFTL | RXFSHR_RXMR |\
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RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
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RXFSHR_RXTCPFCS)
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#define KS_RXFHBCR 0x7E
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#define RXFHBCR_CNT_MASK 0x0FFF
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#define KS_TXQCR 0x80
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#define TXQCR_AETFE (1 << 2)
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#define TXQCR_TXQMAM (1 << 1)
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#define TXQCR_METFE (1 << 0)
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#define KS_RXQCR 0x82
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#define RXQCR_RXDTTS (1 << 12)
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#define RXQCR_RXDBCTS (1 << 11)
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#define RXQCR_RXFCTS (1 << 10)
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#define RXQCR_RXIPHTOE (1 << 9)
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#define RXQCR_RXDTTE (1 << 7)
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#define RXQCR_RXDBCTE (1 << 6)
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#define RXQCR_RXFCTE (1 << 5)
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#define RXQCR_ADRFE (1 << 4)
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#define RXQCR_SDA (1 << 3)
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#define RXQCR_RRXEF (1 << 0)
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#define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
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#define KS_TXFDPR 0x84
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#define TXFDPR_TXFPAI (1 << 14)
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#define TXFDPR_TXFP_MASK (0x7ff << 0)
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#define TXFDPR_TXFP_SHIFT (0)
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#define KS_RXFDPR 0x86
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#define RXFDPR_RXFPAI (1 << 14)
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#define KS_RXDTTR 0x8C
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#define KS_RXDBCTR 0x8E
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#define KS_IER 0x90
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#define KS_ISR 0x92
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#define IRQ_LCI (1 << 15)
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#define IRQ_TXI (1 << 14)
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#define IRQ_RXI (1 << 13)
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#define IRQ_RXOI (1 << 11)
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#define IRQ_TXPSI (1 << 9)
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#define IRQ_RXPSI (1 << 8)
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#define IRQ_TXSAI (1 << 6)
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#define IRQ_RXWFDI (1 << 5)
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#define IRQ_RXMPDI (1 << 4)
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#define IRQ_LDI (1 << 3)
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#define IRQ_EDI (1 << 2)
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#define IRQ_SPIBEI (1 << 1)
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#define IRQ_DEDI (1 << 0)
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#define KS_RXFCTR 0x9C
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#define RXFCTR_THRESHOLD_MASK 0x00FF
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#define KS_RXFC 0x9D
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#define RXFCTR_RXFC_MASK (0xff << 8)
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#define RXFCTR_RXFC_SHIFT (8)
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#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
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#define RXFCTR_RXFCT_MASK (0xff << 0)
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#define RXFCTR_RXFCT_SHIFT (0)
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#define KS_TXNTFSR 0x9E
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#define KS_MAHTR0 0xA0
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#define KS_MAHTR1 0xA2
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#define KS_MAHTR2 0xA4
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#define KS_MAHTR3 0xA6
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#define KS_FCLWR 0xB0
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#define KS_FCHWR 0xB2
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#define KS_FCOWR 0xB4
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#define KS_CIDER 0xC0
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#define CIDER_ID 0x8870
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#define CIDER_REV_MASK (0x7 << 1)
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#define CIDER_REV_SHIFT (1)
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#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
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#define KS_CGCR 0xC6
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#define KS_IACR 0xC8
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#define IACR_RDEN (1 << 12)
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#define IACR_TSEL_MASK (0x3 << 10)
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#define IACR_TSEL_SHIFT (10)
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#define IACR_TSEL_MIB (0x3 << 10)
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#define IACR_ADDR_MASK (0x1f << 0)
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#define IACR_ADDR_SHIFT (0)
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#define KS_IADLR 0xD0
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#define KS_IAHDR 0xD2
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#define KS_PMECR 0xD4
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#define PMECR_PME_DELAY (1 << 14)
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#define PMECR_PME_POL (1 << 12)
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#define PMECR_WOL_WAKEUP (1 << 11)
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#define PMECR_WOL_MAGICPKT (1 << 10)
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#define PMECR_WOL_LINKUP (1 << 9)
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#define PMECR_WOL_ENERGY (1 << 8)
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#define PMECR_AUTO_WAKE_EN (1 << 7)
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#define PMECR_WAKEUP_NORMAL (1 << 6)
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#define PMECR_WKEVT_MASK (0xf << 2)
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#define PMECR_WKEVT_SHIFT (2)
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#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
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#define PMECR_WKEVT_ENERGY (0x1 << 2)
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#define PMECR_WKEVT_LINK (0x2 << 2)
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#define PMECR_WKEVT_MAGICPKT (0x4 << 2)
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#define PMECR_WKEVT_FRAME (0x8 << 2)
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#define PMECR_PM_MASK (0x3 << 0)
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#define PMECR_PM_SHIFT (0)
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#define PMECR_PM_NORMAL (0x0 << 0)
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#define PMECR_PM_ENERGY (0x1 << 0)
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#define PMECR_PM_SOFTDOWN (0x2 << 0)
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#define PMECR_PM_POWERSAVE (0x3 << 0)
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/* Standard MII PHY data */
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#define KS_P1MBCR 0xE4
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#define P1MBCR_FORCE_FDX (1 << 8)
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#define KS_P1MBSR 0xE6
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#define P1MBSR_AN_COMPLETE (1 << 5)
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#define P1MBSR_AN_CAPABLE (1 << 3)
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#define P1MBSR_LINK_UP (1 << 2)
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#define KS_PHY1ILR 0xE8
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#define KS_PHY1IHR 0xEA
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#define KS_P1ANAR 0xEC
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#define KS_P1ANLPR 0xEE
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#define KS_P1SCLMD 0xF4
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#define P1SCLMD_LEDOFF (1 << 15)
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#define P1SCLMD_TXIDS (1 << 14)
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#define P1SCLMD_RESTARTAN (1 << 13)
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#define P1SCLMD_DISAUTOMDIX (1 << 10)
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#define P1SCLMD_FORCEMDIX (1 << 9)
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#define P1SCLMD_AUTONEGEN (1 << 7)
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#define P1SCLMD_FORCE100 (1 << 6)
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#define P1SCLMD_FORCEFDX (1 << 5)
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#define P1SCLMD_ADV_FLOW (1 << 4)
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#define P1SCLMD_ADV_100BT_FDX (1 << 3)
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#define P1SCLMD_ADV_100BT_HDX (1 << 2)
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#define P1SCLMD_ADV_10BT_FDX (1 << 1)
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#define P1SCLMD_ADV_10BT_HDX (1 << 0)
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#define KS_P1CR 0xF6
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#define P1CR_HP_MDIX (1 << 15)
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#define P1CR_REV_POL (1 << 13)
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#define P1CR_OP_100M (1 << 10)
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#define P1CR_OP_FDX (1 << 9)
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#define P1CR_OP_MDI (1 << 7)
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#define P1CR_AN_DONE (1 << 6)
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#define P1CR_LINK_GOOD (1 << 5)
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#define P1CR_PNTR_FLOW (1 << 4)
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#define P1CR_PNTR_100BT_FDX (1 << 3)
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#define P1CR_PNTR_100BT_HDX (1 << 2)
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#define P1CR_PNTR_10BT_FDX (1 << 1)
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#define P1CR_PNTR_10BT_HDX (1 << 0)
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/* TX Frame control */
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#define TXFR_TXIC (1 << 15)
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#define TXFR_TXFID_MASK (0x3f << 0)
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#define TXFR_TXFID_SHIFT (0)
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#define KS_P1SR 0xF8
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#define P1SR_HP_MDIX (1 << 15)
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#define P1SR_REV_POL (1 << 13)
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#define P1SR_OP_100M (1 << 10)
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#define P1SR_OP_FDX (1 << 9)
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#define P1SR_OP_MDI (1 << 7)
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#define P1SR_AN_DONE (1 << 6)
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#define P1SR_LINK_GOOD (1 << 5)
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#define P1SR_PNTR_FLOW (1 << 4)
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#define P1SR_PNTR_100BT_FDX (1 << 3)
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#define P1SR_PNTR_100BT_HDX (1 << 2)
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#define P1SR_PNTR_10BT_FDX (1 << 1)
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#define P1SR_PNTR_10BT_HDX (1 << 0)
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#define ENUM_BUS_NONE 0
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#define ENUM_BUS_8BIT 1
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#define ENUM_BUS_16BIT 2
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#define ENUM_BUS_32BIT 3
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#define MAX_MCAST_LST 32
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#define HW_MCAST_SIZE 8
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#define MAC_ADDR_LEN 6
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/* Chip ID values */
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struct chip_id {
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u16 id;
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char *name;
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};
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#endif
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