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b6e59617c8
The GPIO bank numbers do not appear in the device tree, so make the gpio name based on the address (ie gpio@42110000_25 vs 25) Signed-off-by: chao zeng <chao.zeng@siemens.com>
578 lines
13 KiB
C
578 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* GPIO driver for TI DaVinci DA8xx SOCs.
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*
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* (C) Copyright 2011 Guralp Systems Ltd.
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* Laurence Withers <lwithers@guralp.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "da8xx_gpio.h"
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#if !CONFIG_IS_ENABLED(DM_GPIO)
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#include <asm/arch/hardware.h>
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#include <asm/arch/davinci_misc.h>
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static struct gpio_registry {
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int is_registered;
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char name[GPIO_NAME_SIZE];
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} gpio_registry[MAX_NUM_GPIOS];
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#if defined(CONFIG_SOC_DA8XX)
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#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
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#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
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static const struct pinmux_config gpio_pinmux[] = {
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{ pinmux(13), 8, 6 }, /* GP0[0] */
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{ pinmux(13), 8, 7 },
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{ pinmux(14), 8, 0 },
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{ pinmux(14), 8, 1 },
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{ pinmux(14), 8, 2 },
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{ pinmux(14), 8, 3 },
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{ pinmux(14), 8, 4 },
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{ pinmux(14), 8, 5 },
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{ pinmux(14), 8, 6 },
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{ pinmux(14), 8, 7 },
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{ pinmux(15), 8, 0 },
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{ pinmux(15), 8, 1 },
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{ pinmux(15), 8, 2 },
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{ pinmux(15), 8, 3 },
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{ pinmux(15), 8, 4 },
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{ pinmux(15), 8, 5 },
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{ pinmux(15), 8, 6 }, /* GP1[0] */
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{ pinmux(15), 8, 7 },
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{ pinmux(16), 8, 0 },
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{ pinmux(16), 8, 1 },
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{ pinmux(16), 8, 2 },
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{ pinmux(16), 8, 3 },
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{ pinmux(16), 8, 4 },
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{ pinmux(16), 8, 5 },
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{ pinmux(16), 8, 6 },
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{ pinmux(16), 8, 7 },
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{ pinmux(17), 8, 0 },
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{ pinmux(17), 8, 1 },
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{ pinmux(17), 8, 2 },
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{ pinmux(17), 8, 3 },
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{ pinmux(17), 8, 4 },
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{ pinmux(17), 8, 5 },
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{ pinmux(17), 8, 6 }, /* GP2[0] */
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{ pinmux(17), 8, 7 },
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{ pinmux(18), 8, 0 },
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{ pinmux(18), 8, 1 },
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{ pinmux(18), 8, 2 },
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{ pinmux(18), 8, 3 },
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{ pinmux(18), 8, 4 },
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{ pinmux(18), 8, 5 },
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{ pinmux(18), 8, 6 },
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{ pinmux(18), 8, 7 },
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{ pinmux(19), 8, 0 },
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{ pinmux(9), 8, 2 },
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{ pinmux(9), 8, 3 },
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{ pinmux(9), 8, 4 },
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{ pinmux(9), 8, 5 },
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{ pinmux(9), 8, 6 },
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{ pinmux(10), 8, 1 }, /* GP3[0] */
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{ pinmux(10), 8, 2 },
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{ pinmux(10), 8, 3 },
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{ pinmux(10), 8, 4 },
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{ pinmux(10), 8, 5 },
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{ pinmux(10), 8, 6 },
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{ pinmux(10), 8, 7 },
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{ pinmux(11), 8, 0 },
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{ pinmux(11), 8, 1 },
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{ pinmux(11), 8, 2 },
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{ pinmux(11), 8, 3 },
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{ pinmux(11), 8, 4 },
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{ pinmux(9), 8, 7 },
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{ pinmux(2), 8, 6 },
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{ pinmux(11), 8, 5 },
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{ pinmux(11), 8, 6 },
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{ pinmux(12), 8, 4 }, /* GP4[0] */
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{ pinmux(12), 8, 5 },
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{ pinmux(12), 8, 6 },
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{ pinmux(12), 8, 7 },
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{ pinmux(13), 8, 0 },
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{ pinmux(13), 8, 1 },
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{ pinmux(13), 8, 2 },
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{ pinmux(13), 8, 3 },
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{ pinmux(13), 8, 4 },
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{ pinmux(13), 8, 5 },
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{ pinmux(11), 8, 7 },
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{ pinmux(12), 8, 0 },
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{ pinmux(12), 8, 1 },
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{ pinmux(12), 8, 2 },
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{ pinmux(12), 8, 3 },
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{ pinmux(9), 8, 1 },
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{ pinmux(7), 8, 3 }, /* GP5[0] */
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{ pinmux(7), 8, 4 },
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{ pinmux(7), 8, 5 },
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{ pinmux(7), 8, 6 },
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{ pinmux(7), 8, 7 },
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{ pinmux(8), 8, 0 },
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{ pinmux(8), 8, 1 },
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{ pinmux(8), 8, 2 },
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{ pinmux(8), 8, 3 },
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{ pinmux(8), 8, 4 },
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{ pinmux(8), 8, 5 },
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{ pinmux(8), 8, 6 },
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{ pinmux(8), 8, 7 },
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{ pinmux(9), 8, 0 },
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{ pinmux(7), 8, 1 },
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{ pinmux(7), 8, 2 },
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{ pinmux(5), 8, 1 }, /* GP6[0] */
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{ pinmux(5), 8, 2 },
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{ pinmux(5), 8, 3 },
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{ pinmux(5), 8, 4 },
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{ pinmux(5), 8, 5 },
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{ pinmux(5), 8, 6 },
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{ pinmux(5), 8, 7 },
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{ pinmux(6), 8, 0 },
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{ pinmux(6), 8, 1 },
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{ pinmux(6), 8, 2 },
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{ pinmux(6), 8, 3 },
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{ pinmux(6), 8, 4 },
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{ pinmux(6), 8, 5 },
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{ pinmux(6), 8, 6 },
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{ pinmux(6), 8, 7 },
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{ pinmux(7), 8, 0 },
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{ pinmux(1), 8, 0 }, /* GP7[0] */
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{ pinmux(1), 8, 1 },
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{ pinmux(1), 8, 2 },
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{ pinmux(1), 8, 3 },
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{ pinmux(1), 8, 4 },
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{ pinmux(1), 8, 5 },
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{ pinmux(1), 8, 6 },
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{ pinmux(1), 8, 7 },
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{ pinmux(2), 8, 0 },
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{ pinmux(2), 8, 1 },
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{ pinmux(2), 8, 2 },
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{ pinmux(2), 8, 3 },
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{ pinmux(2), 8, 4 },
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{ pinmux(2), 8, 5 },
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{ pinmux(0), 1, 0 },
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{ pinmux(0), 1, 1 },
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};
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#else /* CONFIG_SOC_DA8XX && CONFIG_SOC_DA850 */
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static const struct pinmux_config gpio_pinmux[] = {
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{ pinmux(1), 8, 7 }, /* GP0[0] */
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{ pinmux(1), 8, 6 },
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{ pinmux(1), 8, 5 },
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{ pinmux(1), 8, 4 },
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{ pinmux(1), 8, 3 },
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{ pinmux(1), 8, 2 },
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{ pinmux(1), 8, 1 },
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{ pinmux(1), 8, 0 },
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{ pinmux(0), 8, 7 },
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{ pinmux(0), 8, 6 },
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{ pinmux(0), 8, 5 },
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{ pinmux(0), 8, 4 },
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{ pinmux(0), 8, 3 },
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{ pinmux(0), 8, 2 },
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{ pinmux(0), 8, 1 },
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{ pinmux(0), 8, 0 },
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{ pinmux(4), 8, 7 }, /* GP1[0] */
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{ pinmux(4), 8, 6 },
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{ pinmux(4), 8, 5 },
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{ pinmux(4), 8, 4 },
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{ pinmux(4), 8, 3 },
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{ pinmux(4), 8, 2 },
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{ pinmux(4), 4, 1 },
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{ pinmux(4), 4, 0 },
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{ pinmux(3), 4, 0 },
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{ pinmux(2), 4, 6 },
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{ pinmux(2), 4, 5 },
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{ pinmux(2), 4, 4 },
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{ pinmux(2), 4, 3 },
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{ pinmux(2), 4, 2 },
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{ pinmux(2), 4, 1 },
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{ pinmux(2), 8, 0 },
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{ pinmux(6), 8, 7 }, /* GP2[0] */
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{ pinmux(6), 8, 6 },
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{ pinmux(6), 8, 5 },
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{ pinmux(6), 8, 4 },
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{ pinmux(6), 8, 3 },
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{ pinmux(6), 8, 2 },
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{ pinmux(6), 8, 1 },
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{ pinmux(6), 8, 0 },
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{ pinmux(5), 8, 7 },
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{ pinmux(5), 8, 6 },
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{ pinmux(5), 8, 5 },
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{ pinmux(5), 8, 4 },
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{ pinmux(5), 8, 3 },
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{ pinmux(5), 8, 2 },
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{ pinmux(5), 8, 1 },
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{ pinmux(5), 8, 0 },
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{ pinmux(8), 8, 7 }, /* GP3[0] */
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{ pinmux(8), 8, 6 },
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{ pinmux(8), 8, 5 },
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{ pinmux(8), 8, 4 },
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{ pinmux(8), 8, 3 },
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{ pinmux(8), 8, 2 },
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{ pinmux(8), 8, 1 },
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{ pinmux(8), 8, 0 },
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{ pinmux(7), 8, 7 },
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{ pinmux(7), 8, 6 },
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{ pinmux(7), 8, 5 },
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{ pinmux(7), 8, 4 },
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{ pinmux(7), 8, 3 },
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{ pinmux(7), 8, 2 },
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{ pinmux(7), 8, 1 },
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{ pinmux(7), 8, 0 },
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{ pinmux(10), 8, 7 }, /* GP4[0] */
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{ pinmux(10), 8, 6 },
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{ pinmux(10), 8, 5 },
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{ pinmux(10), 8, 4 },
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{ pinmux(10), 8, 3 },
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{ pinmux(10), 8, 2 },
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{ pinmux(10), 8, 1 },
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{ pinmux(10), 8, 0 },
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{ pinmux(9), 8, 7 },
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{ pinmux(9), 8, 6 },
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{ pinmux(9), 8, 5 },
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{ pinmux(9), 8, 4 },
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{ pinmux(9), 8, 3 },
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{ pinmux(9), 8, 2 },
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{ pinmux(9), 8, 1 },
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{ pinmux(9), 8, 0 },
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{ pinmux(12), 8, 7 }, /* GP5[0] */
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{ pinmux(12), 8, 6 },
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{ pinmux(12), 8, 5 },
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{ pinmux(12), 8, 4 },
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{ pinmux(12), 8, 3 },
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{ pinmux(12), 8, 2 },
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{ pinmux(12), 8, 1 },
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{ pinmux(12), 8, 0 },
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{ pinmux(11), 8, 7 },
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{ pinmux(11), 8, 6 },
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{ pinmux(11), 8, 5 },
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{ pinmux(11), 8, 4 },
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{ pinmux(11), 8, 3 },
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{ pinmux(11), 8, 2 },
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{ pinmux(11), 8, 1 },
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{ pinmux(11), 8, 0 },
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{ pinmux(19), 8, 6 }, /* GP6[0] */
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{ pinmux(19), 8, 5 },
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{ pinmux(19), 8, 4 },
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{ pinmux(19), 8, 3 },
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{ pinmux(19), 8, 2 },
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{ pinmux(16), 8, 1 },
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{ pinmux(14), 8, 1 },
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{ pinmux(14), 8, 0 },
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{ pinmux(13), 8, 7 },
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{ pinmux(13), 8, 6 },
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{ pinmux(13), 8, 5 },
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{ pinmux(13), 8, 4 },
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{ pinmux(13), 8, 3 },
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{ pinmux(13), 8, 2 },
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{ pinmux(13), 8, 1 },
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{ pinmux(13), 8, 0 },
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{ pinmux(18), 8, 1 }, /* GP7[0] */
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{ pinmux(18), 8, 0 },
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{ pinmux(17), 8, 7 },
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{ pinmux(17), 8, 6 },
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{ pinmux(17), 8, 5 },
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{ pinmux(17), 8, 4 },
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{ pinmux(17), 8, 3 },
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{ pinmux(17), 8, 2 },
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{ pinmux(17), 8, 1 },
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{ pinmux(17), 8, 0 },
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{ pinmux(16), 8, 7 },
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{ pinmux(16), 8, 6 },
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{ pinmux(16), 8, 5 },
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{ pinmux(16), 8, 4 },
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{ pinmux(16), 8, 3 },
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{ pinmux(16), 8, 2 },
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{ pinmux(19), 8, 0 }, /* GP8[0] */
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{ pinmux(3), 4, 7 },
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{ pinmux(3), 4, 6 },
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{ pinmux(3), 4, 5 },
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{ pinmux(3), 4, 4 },
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{ pinmux(3), 4, 3 },
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{ pinmux(3), 4, 2 },
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{ pinmux(2), 4, 7 },
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{ pinmux(19), 8, 1 },
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{ pinmux(19), 8, 0 },
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{ pinmux(18), 8, 7 },
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{ pinmux(18), 8, 6 },
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{ pinmux(18), 8, 5 },
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{ pinmux(18), 8, 4 },
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{ pinmux(18), 8, 3 },
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{ pinmux(18), 8, 2 },
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};
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#endif /* CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850 */
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#else /* !CONFIG_SOC_DA8XX */
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#define davinci_configure_pin_mux(a, b)
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#endif /* CONFIG_SOC_DA8XX */
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int gpio_request(unsigned int gpio, const char *label)
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{
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if (gpio >= MAX_NUM_GPIOS)
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return -1;
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if (gpio_registry[gpio].is_registered)
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return -1;
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gpio_registry[gpio].is_registered = 1;
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strncpy(gpio_registry[gpio].name, label, GPIO_NAME_SIZE);
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gpio_registry[gpio].name[GPIO_NAME_SIZE - 1] = 0;
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davinci_configure_pin_mux(&gpio_pinmux[gpio], 1);
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return 0;
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}
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int gpio_free(unsigned int gpio)
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{
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if (gpio >= MAX_NUM_GPIOS)
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return -1;
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if (!gpio_registry[gpio].is_registered)
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return -1;
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gpio_registry[gpio].is_registered = 0;
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gpio_registry[gpio].name[0] = '\0';
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/* Do not configure as input or change pin mux here */
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return 0;
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}
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#endif
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static int _gpio_direction_input(struct davinci_gpio *bank, unsigned int gpio)
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{
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setbits_le32(&bank->dir, 1U << GPIO_BIT(gpio));
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return 0;
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}
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static int _gpio_get_value(struct davinci_gpio *bank, unsigned int gpio)
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{
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unsigned int ip;
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ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gpio));
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return ip ? 1 : 0;
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}
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static int _gpio_set_value(struct davinci_gpio *bank, unsigned int gpio, int value)
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{
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if (value)
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bank->set_data = 1U << GPIO_BIT(gpio);
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else
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bank->clr_data = 1U << GPIO_BIT(gpio);
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return 0;
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}
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static int _gpio_get_dir(struct davinci_gpio *bank, unsigned int gpio)
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{
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return in_le32(&bank->dir) & (1U << GPIO_BIT(gpio));
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}
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static int _gpio_direction_output(struct davinci_gpio *bank, unsigned int gpio,
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int value)
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{
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clrbits_le32(&bank->dir, 1U << GPIO_BIT(gpio));
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_gpio_set_value(bank, gpio, value);
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return 0;
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}
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#if !CONFIG_IS_ENABLED(DM_GPIO)
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void gpio_info(void)
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{
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unsigned int gpio, dir, val;
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struct davinci_gpio *bank;
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for (gpio = 0; gpio < MAX_NUM_GPIOS; ++gpio) {
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bank = GPIO_BANK(gpio);
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dir = _gpio_get_dir(bank, gpio);
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val = gpio_get_value(gpio);
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printf("% 4d: %s: %d [%c] %s\n",
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gpio, dir ? " in" : "out", val,
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gpio_registry[gpio].is_registered ? 'x' : ' ',
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gpio_registry[gpio].name);
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}
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}
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int gpio_direction_input(unsigned int gpio)
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{
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struct davinci_gpio *bank;
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bank = GPIO_BANK(gpio);
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return _gpio_direction_input(bank, gpio);
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}
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int gpio_direction_output(unsigned int gpio, int value)
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{
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struct davinci_gpio *bank;
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bank = GPIO_BANK(gpio);
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return _gpio_direction_output(bank, gpio, value);
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}
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int gpio_get_value(unsigned int gpio)
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{
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struct davinci_gpio *bank;
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bank = GPIO_BANK(gpio);
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return _gpio_get_value(bank, gpio);
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}
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int gpio_set_value(unsigned int gpio, int value)
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{
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struct davinci_gpio *bank;
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bank = GPIO_BANK(gpio);
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return _gpio_set_value(bank, gpio, value);
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}
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#else /* DM_GPIO */
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static struct davinci_gpio *davinci_get_gpio_bank(struct udevice *dev, unsigned int offset)
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{
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struct davinci_gpio_bank *bank = dev_get_priv(dev);
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unsigned long addr;
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/*
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* The device tree is not broken into banks but the infrastructure is
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* expecting it this way, so we'll first include the 0x10 offset, then
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* calculate the bank manually based on the offset.
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* Casting 'addr' as Unsigned long is needed to make the math work.
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*/
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addr = ((unsigned long)(struct davinci_gpio *)bank->base) +
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0x10 + (0x28 * (offset >> 5));
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return (struct davinci_gpio *)addr;
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}
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static int davinci_gpio_direction_input(struct udevice *dev, unsigned int offset)
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{
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struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
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/*
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* Fetch the address based on GPIO, but only pass the masked low 32-bits
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*/
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_gpio_direction_input(base, (offset & 0x1f));
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return 0;
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}
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static int davinci_gpio_direction_output(struct udevice *dev, unsigned int offset,
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int value)
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{
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struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
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_gpio_direction_output(base, (offset & 0x1f), value);
|
|
return 0;
|
|
}
|
|
|
|
static int davinci_gpio_get_value(struct udevice *dev, unsigned int offset)
|
|
{
|
|
struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
|
|
|
|
return _gpio_get_value(base, (offset & 0x1f));
|
|
}
|
|
|
|
static int davinci_gpio_set_value(struct udevice *dev, unsigned int offset,
|
|
int value)
|
|
{
|
|
struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
|
|
|
|
_gpio_set_value(base, (offset & 0x1f), value);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int davinci_gpio_get_function(struct udevice *dev, unsigned int offset)
|
|
{
|
|
unsigned int dir;
|
|
struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
|
|
|
|
dir = _gpio_get_dir(base, offset);
|
|
|
|
if (dir)
|
|
return GPIOF_INPUT;
|
|
|
|
return GPIOF_OUTPUT;
|
|
}
|
|
|
|
static int davinci_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
|
|
struct ofnode_phandle_args *args)
|
|
{
|
|
desc->offset = args->args[0];
|
|
|
|
if (args->args[1] & GPIO_ACTIVE_LOW)
|
|
desc->flags = GPIOD_ACTIVE_LOW;
|
|
else
|
|
desc->flags = 0;
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_gpio_ops gpio_davinci_ops = {
|
|
.direction_input = davinci_gpio_direction_input,
|
|
.direction_output = davinci_gpio_direction_output,
|
|
.get_value = davinci_gpio_get_value,
|
|
.set_value = davinci_gpio_set_value,
|
|
.get_function = davinci_gpio_get_function,
|
|
.xlate = davinci_gpio_xlate,
|
|
};
|
|
|
|
static int davinci_gpio_probe(struct udevice *dev)
|
|
{
|
|
struct davinci_gpio_bank *bank = dev_get_priv(dev);
|
|
struct davinci_gpio_plat *plat = dev_get_plat(dev);
|
|
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
const void *fdt = gd->fdt_blob;
|
|
int node = dev_of_offset(dev);
|
|
|
|
uc_priv->bank_name = plat->port_name;
|
|
uc_priv->gpio_count = fdtdec_get_int(fdt, node, "ti,ngpio", -1);
|
|
bank->base = (struct davinci_gpio *)plat->base;
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id davinci_gpio_ids[] = {
|
|
{ .compatible = "ti,dm6441-gpio" },
|
|
{ .compatible = "ti,k2g-gpio" },
|
|
{ .compatible = "ti,keystone-gpio" },
|
|
{ }
|
|
};
|
|
|
|
static int davinci_gpio_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct davinci_gpio_plat *plat = dev_get_plat(dev);
|
|
fdt_addr_t addr;
|
|
char name[18], *str;
|
|
|
|
addr = dev_read_addr(dev);
|
|
if (addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
plat->base = addr;
|
|
|
|
sprintf(name, "gpio@%4x_", (unsigned int)plat->base);
|
|
str = strdup(name);
|
|
if (!str)
|
|
return -ENOMEM;
|
|
plat->port_name = str;
|
|
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_DRIVER(ti_dm6441_gpio) = {
|
|
.name = "ti_dm6441_gpio",
|
|
.id = UCLASS_GPIO,
|
|
.ops = &gpio_davinci_ops,
|
|
.of_to_plat = of_match_ptr(davinci_gpio_of_to_plat),
|
|
.of_match = davinci_gpio_ids,
|
|
.bind = dm_scan_fdt_dev,
|
|
.plat_auto = sizeof(struct davinci_gpio_plat),
|
|
.probe = davinci_gpio_probe,
|
|
.priv_auto = sizeof(struct davinci_gpio_bank),
|
|
};
|
|
|
|
#endif
|