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23c83366f3
Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) Samuel Holland <samuel@sholland.org>
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/sun8i-r-ccu.h>
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#include <dt-bindings/reset/sun8i-r-ccu.h>
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#include <linux/bitops.h>
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static struct ccu_clk_gate a31_r_gates[] = {
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[CLK_APB0_PIO] = GATE(0x028, BIT(0)),
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[CLK_APB0_IR] = GATE(0x028, BIT(1)),
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[CLK_APB0_TIMER] = GATE(0x028, BIT(2)),
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[CLK_APB0_RSB] = GATE(0x028, BIT(3)),
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[CLK_APB0_UART] = GATE(0x028, BIT(4)),
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[CLK_APB0_I2C] = GATE(0x028, BIT(6)),
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[CLK_APB0_TWD] = GATE(0x028, BIT(7)),
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};
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static struct ccu_reset a31_r_resets[] = {
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[RST_APB0_IR] = RESET(0x0b0, BIT(1)),
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[RST_APB0_TIMER] = RESET(0x0b0, BIT(2)),
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[RST_APB0_RSB] = RESET(0x0b0, BIT(3)),
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[RST_APB0_UART] = RESET(0x0b0, BIT(4)),
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[RST_APB0_I2C] = RESET(0x0b0, BIT(6)),
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};
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static const struct ccu_desc a31_r_ccu_desc = {
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.gates = a31_r_gates,
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.resets = a31_r_resets,
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};
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static int a31_r_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
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}
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static const struct udevice_id a31_r_clk_ids[] = {
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{ .compatible = "allwinner,sun8i-a83t-r-ccu",
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.data = (ulong)&a31_r_ccu_desc },
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{ .compatible = "allwinner,sun8i-h3-r-ccu",
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.data = (ulong)&a31_r_ccu_desc },
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{ .compatible = "allwinner,sun50i-a64-r-ccu",
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.data = (ulong)&a31_r_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun6i_a31_r) = {
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.name = "sun6i_a31_r_ccu",
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.id = UCLASS_CLK,
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.of_match = a31_r_clk_ids,
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.priv_auto = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = a31_r_clk_bind,
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};
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