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	Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
		
			
				
	
	
		
			58 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			58 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2013 Boundary Devices Inc.
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| #ifndef __ASM_ARCH_MX6Q_DDR_H__
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| #define __ASM_ARCH_MX6Q_DDR_H__
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| 
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| #ifndef CONFIG_MX6Q
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| #error "wrong CPU"
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| #endif
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| 
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| #define MX6_IOM_DRAM_DQM0	0x020e05ac
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| #define MX6_IOM_DRAM_DQM1	0x020e05b4
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| #define MX6_IOM_DRAM_DQM2	0x020e0528
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| #define MX6_IOM_DRAM_DQM3	0x020e0520
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| #define MX6_IOM_DRAM_DQM4	0x020e0514
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| #define MX6_IOM_DRAM_DQM5	0x020e0510
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| #define MX6_IOM_DRAM_DQM6	0x020e05bc
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| #define MX6_IOM_DRAM_DQM7	0x020e05c4
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| 
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| #define MX6_IOM_DRAM_CAS	0x020e056c
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| #define MX6_IOM_DRAM_RAS	0x020e0578
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| #define MX6_IOM_DRAM_RESET	0x020e057c
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| #define MX6_IOM_DRAM_SDCLK_0	0x020e0588
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| #define MX6_IOM_DRAM_SDCLK_1	0x020e0594
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| #define MX6_IOM_DRAM_SDBA2	0x020e058c
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| #define MX6_IOM_DRAM_SDCKE0	0x020e0590
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| #define MX6_IOM_DRAM_SDCKE1	0x020e0598
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| #define MX6_IOM_DRAM_SDODT0	0x020e059c
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| #define MX6_IOM_DRAM_SDODT1	0x020e05a0
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| 
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| #define MX6_IOM_DRAM_SDQS0	0x020e05a8
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| #define MX6_IOM_DRAM_SDQS1	0x020e05b0
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| #define MX6_IOM_DRAM_SDQS2	0x020e0524
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| #define MX6_IOM_DRAM_SDQS3	0x020e051c
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| #define MX6_IOM_DRAM_SDQS4	0x020e0518
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| #define MX6_IOM_DRAM_SDQS5	0x020e050c
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| #define MX6_IOM_DRAM_SDQS6	0x020e05b8
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| #define MX6_IOM_DRAM_SDQS7	0x020e05c0
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| 
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| #define MX6_IOM_GRP_B0DS	0x020e0784
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| #define MX6_IOM_GRP_B1DS	0x020e0788
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| #define MX6_IOM_GRP_B2DS	0x020e0794
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| #define MX6_IOM_GRP_B3DS	0x020e079c
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| #define MX6_IOM_GRP_B4DS	0x020e07a0
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| #define MX6_IOM_GRP_B5DS	0x020e07a4
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| #define MX6_IOM_GRP_B6DS	0x020e07a8
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| #define MX6_IOM_GRP_B7DS	0x020e0748
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| #define MX6_IOM_GRP_ADDDS	0x020e074c
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| #define MX6_IOM_DDRMODE_CTL	0x020e0750
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| #define MX6_IOM_GRP_DDRPKE	0x020e0758
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| #define MX6_IOM_GRP_DDRMODE	0x020e0774
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| #define MX6_IOM_GRP_CTLDS	0x020e078c
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| #define MX6_IOM_GRP_DDR_TYPE	0x020e0798
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| 
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| #endif	/*__ASM_ARCH_MX6Q_DDR_H__ */
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