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1e43bb6732
The optimized memset uses the dc opcode, which causes problems when the cache is disabled. This patch adds a check if the cache is disabled and uses a very simple memset implementation in this case. Otherwise the optimized version is used. Signed-off-by: Stefan Roese <sr@denx.de>
149 lines
2.8 KiB
ArmAsm
149 lines
2.8 KiB
ArmAsm
/* SPDX-License-Identifier: MIT */
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/*
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* memset - fill memory with a constant byte
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*
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* Copyright (c) 2012-2021, Arm Limited.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
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*
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*/
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#include <asm/macro.h>
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#include "asmdefs.h"
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#define dstin x0
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#define val x1
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#define valw w1
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#define count x2
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#define dst x3
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#define dstend x4
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#define zva_val x5
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ENTRY (memset)
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PTR_ARG (0)
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SIZE_ARG (2)
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/*
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* The optimized memset uses the dc opcode, which causes problems
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* when the cache is disabled. Let's check if the cache is disabled
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* and use a very simple memset implementation in this case. Otherwise
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* jump to the optimized version.
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*/
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switch_el x6, 3f, 2f, 1f
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3: mrs x6, sctlr_el3
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b 0f
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2: mrs x6, sctlr_el2
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b 0f
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1: mrs x6, sctlr_el1
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0:
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tst x6, #CR_C
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bne 9f
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/*
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* A very "simple" memset implementation without the use of the
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* dc opcode. Can be run with caches disabled.
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*/
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mov x3, #0x0
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cmp count, x3 /* check for zero length */
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beq 8f
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4: strb valw, [dstin, x3]
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add x3, x3, #0x1
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cmp count, x3
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bne 4b
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8: ret
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9:
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/* Here the optimized memset version starts */
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dup v0.16B, valw
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add dstend, dstin, count
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cmp count, 96
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b.hi L(set_long)
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cmp count, 16
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b.hs L(set_medium)
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mov val, v0.D[0]
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/* Set 0..15 bytes. */
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tbz count, 3, 1f
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str val, [dstin]
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str val, [dstend, -8]
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ret
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.p2align 4
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1: tbz count, 2, 2f
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str valw, [dstin]
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str valw, [dstend, -4]
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ret
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2: cbz count, 3f
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strb valw, [dstin]
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tbz count, 1, 3f
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strh valw, [dstend, -2]
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3: ret
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/* Set 17..96 bytes. */
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L(set_medium):
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str q0, [dstin]
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tbnz count, 6, L(set96)
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str q0, [dstend, -16]
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tbz count, 5, 1f
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str q0, [dstin, 16]
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str q0, [dstend, -32]
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1: ret
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.p2align 4
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/* Set 64..96 bytes. Write 64 bytes from the start and
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32 bytes from the end. */
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L(set96):
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str q0, [dstin, 16]
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stp q0, q0, [dstin, 32]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 4
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L(set_long):
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and valw, valw, 255
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bic dst, dstin, 15
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str q0, [dstin]
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cmp count, 160
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ccmp valw, 0, 0, hs
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b.ne L(no_zva)
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#ifndef SKIP_ZVA_CHECK
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mrs zva_val, dczid_el0
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and zva_val, zva_val, 31
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cmp zva_val, 4 /* ZVA size is 64 bytes. */
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b.ne L(no_zva)
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#endif
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str q0, [dst, 16]
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stp q0, q0, [dst, 32]
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bic dst, dst, 63
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sub count, dstend, dst /* Count is now 64 too large. */
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sub count, count, 128 /* Adjust count and bias for loop. */
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.p2align 4
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L(zva_loop):
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add dst, dst, 64
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dc zva, dst
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subs count, count, 64
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b.hi L(zva_loop)
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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L(no_zva):
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sub count, dstend, dst /* Count is 16 too large. */
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sub dst, dst, 16 /* Dst is biased by -32. */
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sub count, count, 64 + 16 /* Adjust count and bias for loop. */
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L(no_zva_loop):
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stp q0, q0, [dst, 32]
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stp q0, q0, [dst, 64]!
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subs count, count, 64
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b.hi L(no_zva_loop)
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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END (memset)
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