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	This converts the following to Kconfig: CONFIG_SYS_FSL_CPC CONFIG_SYS_CPC_REINIT_F Signed-off-by: Tom Rini <trini@konsulko.com>
		
			
				
	
	
		
			75 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			75 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /*
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|  * Copyright 2010-2011 Freescale Semiconductor, Inc.
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|  */
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| 
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| #ifndef __FSL_SECURE_BOOT_H
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| #define __FSL_SECURE_BOOT_H
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| #include <asm/config_mpc85xx.h>
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| 
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| #ifdef CONFIG_NXP_ESBC
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| #if defined(CONFIG_FSL_CORENET)
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| #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
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| #else
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| #define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
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| #endif
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| #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
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| 
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| #if defined(CONFIG_TARGET_T2080QDS) || \
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| 	defined(CONFIG_TARGET_T2080RDB) || \
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| 	defined(CONFIG_TARGET_T1042RDB) || \
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| 	defined(CONFIG_TARGET_T1042D4RDB) || \
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| 	defined(CONFIG_TARGET_T1042RDB_PI) || \
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| 	defined(CONFIG_ARCH_T1024)
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| #undef CONFIG_SYS_INIT_L3_ADDR
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| #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
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| #endif
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| 
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| #if defined(CONFIG_RAMBOOT_PBL)
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| #undef CONFIG_SYS_INIT_L3_ADDR
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| #ifdef CONFIG_SYS_INIT_L3_VADDR
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| #define CONFIG_SYS_INIT_L3_ADDR	\
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| 			(CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
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| 					0xbff00000
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| #else
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| #define CONFIG_SYS_INIT_L3_ADDR		0xbff00000
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| #endif
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| #endif
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| 
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| #if defined(CONFIG_ARCH_P3041)	||	\
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| 	defined(CONFIG_ARCH_P4080) ||	\
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| 	defined(CONFIG_ARCH_P5040) ||	\
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| 	defined(CONFIG_ARCH_P2041)
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| 	#define	CONFIG_FSL_TRUST_ARCH_v1
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| #endif
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| 
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| #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
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| /* The key used for verification of next level images
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|  * is picked up from an Extension Table which has
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|  * been verified by the ISBC (Internal Secure boot Code)
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|  * in boot ROM of the SoC.
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|  * The feature is only applicable in case of NOR boot and is
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|  * not applicable in case of RAMBOOT (NAND, SD, SPI).
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|  */
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| #define CONFIG_FSL_ISBC_KEY_EXT
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| #endif
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| #endif /* #ifdef CONFIG_NXP_ESBC */
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| 
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| #ifdef CONFIG_CHAIN_OF_TRUST
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| #ifdef CONFIG_SPL_BUILD
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| /*
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|  * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
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|  * due to space crunch on CPC and thus malloc will not work.
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|  */
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| #define CONFIG_SPL_PPAACT_ADDR		0x2e000000
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| #define CONFIG_SPL_SPAACT_ADDR		0x2f000000
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| #define CONFIG_SPL_JR0_LIODN_S		454
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| #define CONFIG_SPL_JR0_LIODN_NS		458
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| #endif /* ifdef CONFIG_SPL_BUILD */
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| 
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| #ifndef CONFIG_SPL_BUILD
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| #include <config_fsl_chain_trust.h>
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| #endif /* #ifndef CONFIG_SPL_BUILD */
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| #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
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| #endif
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