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	- support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
		
			
				
	
	
		
			115 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			115 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright 2008 Freescale Semiconductor, Inc.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License
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|  * Version 2 as published by the Free Software Foundation.
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|  */
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| 
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| #include <common.h>
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| #include <ddr_spd.h>
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| 
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| /* used for ddr1 and ddr2 spd */
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| static int
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| spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum)
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| {
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| 	unsigned int cksum = 0;
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| 	unsigned int i;
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| 
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| 	/*
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| 	 * Check SPD revision supported
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| 	 * Rev 1.2 or less supported by this code
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| 	 */
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| 	if (spd_rev > 0x12) {
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| 		printf("SPD revision %02X not supported by this code\n",
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| 		       spd_rev);
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| 		return 1;
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| 	}
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| 
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| 	/*
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| 	 * Calculate checksum
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| 	 */
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| 	for (i = 0; i < 63; i++) {
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| 		cksum += *buf++;
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| 	}
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| 	cksum &= 0xFF;
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| 
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| 	if (cksum != spd_cksum) {
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| 		printf("SPD checksum unexpected. "
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| 			"Checksum in SPD = %02X, computed SPD = %02X\n",
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| 			spd_cksum, cksum);
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| 		return 1;
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| unsigned int
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| ddr1_spd_check(const ddr1_spd_eeprom_t *spd)
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| {
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| 	const u8 *p = (const u8 *)spd;
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| 
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| 	return spd_check(p, spd->spd_rev, spd->cksum);
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| }
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| 
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| unsigned int
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| ddr2_spd_check(const ddr2_spd_eeprom_t *spd)
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| {
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| 	const u8 *p = (const u8 *)spd;
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| 
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| 	return spd_check(p, spd->spd_rev, spd->cksum);
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| }
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| 
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| /*
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|  * CRC16 compute for DDR3 SPD
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|  * Copied from DDR3 SPD spec.
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|  */
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| static int
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| crc16(char *ptr, int count)
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| {
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| 	int crc, i;
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| 
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| 	crc = 0;
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| 	while (--count >= 0) {
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| 		crc = crc ^ (int)*ptr++ << 8;
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| 		for (i = 0; i < 8; ++i)
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| 			if (crc & 0x8000)
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| 				crc = crc << 1 ^ 0x1021;
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| 			else
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| 				crc = crc << 1;
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| 	}
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| 	return crc & 0xffff;
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| }
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| 
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| unsigned int
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| ddr3_spd_check(const ddr3_spd_eeprom_t *spd)
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| {
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| 	char *p = (char *)spd;
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| 	int csum16;
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| 	int len;
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| 	char crc_lsb;	/* byte 126 */
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| 	char crc_msb;	/* byte 127 */
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| 
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| 	/*
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| 	 * SPD byte0[7] - CRC coverage
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| 	 * 0 = CRC covers bytes 0~125
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| 	 * 1 = CRC covers bytes 0~116
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| 	 */
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| 
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| 	len = !(spd->info_size_crc & 0x80) ? 126 : 117;
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| 	csum16 = crc16(p, len);
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| 
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| 	crc_lsb = (char) (csum16 & 0xff);
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| 	crc_msb = (char) (csum16 >> 8);
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| 
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| 	if (spd->crc[0] == crc_lsb && spd->crc[1] == crc_msb) {
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| 		return 0;
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| 	} else {
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| 		printf("SPD checksum unexpected.\n"
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| 			"Checksum lsb in SPD = %02X, computed SPD = %02X\n"
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| 			"Checksum msb in SPD = %02X, computed SPD = %02X\n",
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| 			spd->crc[0], crc_lsb, spd->crc[1], crc_msb);
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| 		return 1;
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| 	}
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| }
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