Sumit Garg 9781d9ff5f armv8: layerscape: Allocate 66 MB DDR for secure memory ...

Change DDR allocated for secure memory from 2 MB to 66 MB. This
additional 64 MB secure memory is required for trusted OS running
in Trusted Execution Environment using ARMv8 TrustZone.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

2017-10-27 08:47:14 -07:00

..

clock.h

common: freescale: Move arch-specific declarations

2017-06-05 12:30:55 -04:00

config.h

armv8: layerscape: Allocate 66 MB DDR for secure memory

2017-10-27 08:47:14 -07:00

cpu.h

armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC

2017-09-22 12:45:17 -07:00

fdt.h

armv8/layerscape: remove unnecessary function declares

2017-01-18 09:24:51 -08:00

fsl_serdes.h

armv8: fsl-layerscape: Support to add RGMII for ls1088aqds

2017-09-11 08:01:05 -07:00

immap_lsch2.h

armv8: Add workaround for USB erratum A-009007

2017-09-11 08:01:06 -07:00

immap_lsch3.h

armv8: ls1088a: fix the MMU table for pcie config space

2017-09-11 08:01:07 -07:00

imx-regs.h

serial: lpuart: restructure lpuart driver

2017-03-17 09:27:08 +01:00

mmu.h

armv8: layerscape: Update early MMU for DDR after initialization

2017-03-14 08:44:03 -07:00

mp.h

armv8: Remove duplicate definition for IH_ARCH_ARM and IH_ARCH_ARM64

2017-08-01 08:28:56 -07:00

ns_access.h

fsl: csu: add an API to set R/W permission to PCIe

2016-09-14 14:07:08 -07:00

ppa.h

fsl-layerscape/ppa: cleanup ppa.h

2017-03-28 08:59:47 -07:00

soc.h

armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()

2017-09-11 08:01:05 -07:00

speed.h

armv8/fsl_lsch3: Change arch to fsl-layerscape

2015-10-29 10:34:00 -07:00

stream_id_lsch2.h

arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2

2017-03-28 10:47:16 -07:00

stream_id_lsch3.h

armv8: ls1088a: Add NXP LS1088A SoC support

2017-09-11 08:00:13 -07:00