Ye Li 971a71e114 i.MX7ULP: Change clock rate calculation for NIC1 BUS and EXT ...

On i.MX7ULP B0, there is change in NIC clock dividers architecture.
On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but
on B0 they are parallel with NIC1 DIV. So now the dividers are independent.
This patch modifies the scg_nic_get_rate function according to this change.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>

2019-10-08 16:35:16 +02:00

..

clock.c

i.MX7ULP: Set A7 core frequency to 500Mhz for B0 chip

2019-10-08 16:35:16 +02:00

iomux.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

Kconfig

i.MX7ULP: Add CONFIG_MX7ULP to kconfig

2019-10-08 16:35:16 +02:00

Makefile

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

pcc.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

scg.c

i.MX7ULP: Change clock rate calculation for NIC1 BUS and EXT

2019-10-08 16:35:16 +02:00

soc.c

i.MX7ULP: Add CPU revision check for B0

2019-10-08 16:35:16 +02:00