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2c451f7831
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com>
57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _UTILS_H_
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#define _UTILS_H_
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static inline s32 log_2_n_round_up(u32 n)
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{
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s32 log2n = -1;
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u32 temp = n;
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while (temp) {
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log2n++;
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temp >>= 1;
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}
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if (n & (n - 1))
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return log2n + 1; /* not power of 2 - round up */
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else
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return log2n; /* power of 2 */
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}
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static inline s32 log_2_n_round_down(u32 n)
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{
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s32 log2n = -1;
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u32 temp = n;
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while (temp) {
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log2n++;
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temp >>= 1;
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}
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return log2n;
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}
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#endif
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