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Benoît Thébaudeau 1791b1f97f imx: mx6q DDR3 init: Fix RST_to_CKE 
MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded
as 0x23 for the bit-field MMDC1_MDOR[5:0].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12 13:52:31 +01:00
..
mx6q_4x_mt41j128.cfg
imx: mx6q DDR3 init: Fix RST_to_CKE
2013-02-12 13:52:31 +01:00