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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
60 lines
1.3 KiB
C
60 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*/
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#include <init.h>
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#include <time.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pit.h>
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#include <asm/arch/clk.h>
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#include <div64.h>
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#if !defined(CONFIG_AT91FAMILY)
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# error You need to define CONFIG_AT91FAMILY in your board config!
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
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* setting the 20 bit counter period to its maximum (0xfffff).
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* (See the relevant data sheets to understand that this really works)
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*
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* We do also mimic the typical powerpc way of incrementing
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* two 32 bit registers called tbl and tbu.
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*
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* Those registers increment at 1/16 the main clock rate.
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*/
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#define TIMER_LOAD_VAL 0xfffff
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/*
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* Use the PITC in full 32 bit incrementing mode
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*/
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int timer_init(void)
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{
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at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
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at91_periph_clk_enable(ATMEL_ID_SYS);
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/* Enable PITC */
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writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
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gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
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return 0;
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}
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/*
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* Return the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return gd->arch.timer_rate_hz;
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}
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