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8ed5885693
This adds a driver for the SPI controller found on davinci based SoCs from Texas Instruments. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
102 lines
2.6 KiB
C
102 lines
2.6 KiB
C
/*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Register definitions for the DaVinci SPI Controller
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _DAVINCI_SPI_H_
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#define _DAVINCI_SPI_H_
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struct davinci_spi_regs {
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dv_reg gcr0; /* 0x00 */
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dv_reg gcr1; /* 0x04 */
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dv_reg int0; /* 0x08 */
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dv_reg lvl; /* 0x0c */
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dv_reg flg; /* 0x10 */
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dv_reg pc0; /* 0x14 */
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dv_reg pc1; /* 0x18 */
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dv_reg pc2; /* 0x1c */
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dv_reg pc3; /* 0x20 */
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dv_reg pc4; /* 0x24 */
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dv_reg pc5; /* 0x28 */
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dv_reg rsvd[3];
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dv_reg dat0; /* 0x38 */
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dv_reg dat1; /* 0x3c */
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dv_reg buf; /* 0x40 */
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dv_reg emu; /* 0x44 */
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dv_reg delay; /* 0x48 */
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dv_reg def; /* 0x4c */
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dv_reg fmt0; /* 0x50 */
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dv_reg fmt1; /* 0x54 */
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dv_reg fmt2; /* 0x58 */
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dv_reg fmt3; /* 0x5c */
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dv_reg intvec0; /* 0x60 */
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dv_reg intvec1; /* 0x64 */
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};
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#define BIT(x) (1 << (x))
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/* SPIGCR0 */
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#define SPIGCR0_SPIENA_MASK 0x1
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#define SPIGCR0_SPIRST_MASK 0x0
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/* SPIGCR0 */
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#define SPIGCR1_CLKMOD_MASK BIT(1)
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#define SPIGCR1_MASTER_MASK BIT(0)
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#define SPIGCR1_SPIENA_MASK BIT(24)
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/* SPIPC0 */
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#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
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#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
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#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
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#define SPIPC0_EN0FUN_MASK BIT(0)
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/* SPIFMT0 */
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#define SPIFMT_SHIFTDIR_SHIFT 20
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#define SPIFMT_POLARITY_SHIFT 17
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#define SPIFMT_PHASE_SHIFT 16
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#define SPIFMT_PRESCALE_SHIFT 8
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/* SPIDAT1 */
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#define SPIDAT1_CSHOLD_SHIFT 28
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#define SPIDAT1_CSNR_SHIFT 16
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/* SPIDELAY */
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#define SPI_C2TDELAY_SHIFT 24
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#define SPI_T2CDELAY_SHIFT 16
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/* SPIBUF */
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#define SPIBUF_RXEMPTY_MASK BIT(31)
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#define SPIBUF_TXFULL_MASK BIT(29)
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/* SPIDEF */
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#define SPIDEF_CSDEF0_MASK BIT(0)
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struct davinci_spi_slave {
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struct spi_slave slave;
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struct davinci_spi_regs *regs;
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unsigned int freq;
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};
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static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct davinci_spi_slave, slave);
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}
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#endif /* _DAVINCI_SPI_H_ */
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