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b4b266fc13
The MediaTek MT7987/MT7988 SoCs features a built-in 2.5Gb PHY
connected to GMAC1. The PHY supports 10/100/1000/2500 Mbps
full-duplex only.
The PHY requires one or two firmware files. Firmware for MT7988 has
already been added to upstream: mediatek/mt7988/i2p5ge-phy-pmb.bin.
MT7987 has two firmware files which will be add to upstream later:
i2p5ge-phy-pmb.bin and i2p5ge-phy-DSPBitTb.bin.
Environment variable can be set for firmware data loading:
mt7987_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
mt7987_i2p5ge_load_dspbit_firmware for i2p5ge-phy-DSPBitTb.bin
mt7988_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
This driver allows dedicated weak functions to be overridden by
board to provide the firmware data:
mt7987_i2p5ge_get_fw() for MT7987
mt7988_i2p5ge_get_fw() for MT7988
To enable the PHY, add the following not to device tree:
ð1 {
status = "okay";
phy-mode = "xgmii";
phy-handle = <&phy15>;
phy15: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
phy-mode = "xgmii";
};
};
Signed-off-by: Sky Huang <SkyLake.Huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
104 lines
3.7 KiB
C
104 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2025 MediaTek Inc. All Rights Reserved.
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*
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* Author: Sky Huang <SkyLake.Huang@mediatek.com>
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*
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* Common definition for Mediatek Ethernet PHYs
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*/
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#ifndef _MTK_EPHY_H_
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#define _MTK_EPHY_H_
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#define MTK_EXT_PAGE_ACCESS 0x1f
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#define MTK_PHY_PAGE_STANDARD 0x0000
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#define MTK_PHY_PAGE_EXTENDED_1 0x0001
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#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
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/* suprv_media_select_RefClk */
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#define MTK_PHY_LP_DETECTED_MASK GENMASK(7, 6)
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#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
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#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
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/* Registers on Token Ring debug nodes */
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/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x2 */
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#define AN_STATE_MASK GENMASK(22, 19)
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#define AN_STATE_SHIFT 19
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#define AN_STATE_TX_DISABLE 1
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/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
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#define AN_NEW_LP_CNT_LIMIT_MASK GENMASK(23, 20)
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#define AUTO_NP_10XEN BIT(6)
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/* Registers on MDIO_MMD_VEND1 */
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#define MTK_PHY_LINK_STATUS_MISC (0xa2)
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#define MTK_PHY_FINAL_SPEED_1000 BIT(3)
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/* Registers on MDIO_MMD_VEND2 */
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#define MTK_PHY_LED0_ON_CTRL 0x24
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#define MTK_PHY_LED1_ON_CTRL 0x26
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#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0)
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#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0)
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#define MTK_PHY_LED_ON_LINK1000 BIT(0)
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#define MTK_PHY_LED_ON_LINK100 BIT(1)
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#define MTK_PHY_LED_ON_LINK10 BIT(2)
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#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
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#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
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#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
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#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
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#define MTK_PHY_LED_ON_LINK2500 BIT(7)
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#define MTK_PHY_LED_ON_POLARITY BIT(14)
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#define MTK_PHY_LED_ON_ENABLE BIT(15)
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#define MTK_PHY_LED0_BLINK_CTRL 0x25
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#define MTK_PHY_LED1_BLINK_CTRL 0x27
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#define MTK_PHY_LED_BLINK_1000TX BIT(0)
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#define MTK_PHY_LED_BLINK_1000RX BIT(1)
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#define MTK_PHY_LED_BLINK_100TX BIT(2)
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#define MTK_PHY_LED_BLINK_100RX BIT(3)
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#define MTK_PHY_LED_BLINK_10TX BIT(4)
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#define MTK_PHY_LED_BLINK_10RX BIT(5)
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#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
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#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
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#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
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#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
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#define MTK_PHY_LED_BLINK_2500TX BIT(10)
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#define MTK_PHY_LED_BLINK_2500RX BIT(11)
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#define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \
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MTK_PHY_LED_ON_LINK100 | \
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MTK_PHY_LED_ON_LINK10)
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#define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
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MTK_PHY_LED_BLINK_100RX | \
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MTK_PHY_LED_BLINK_10RX)
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#define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
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MTK_PHY_LED_BLINK_100RX | \
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MTK_PHY_LED_BLINK_10RX)
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#define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \
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MTK_GPHY_LED_ON_SET)
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#define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
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MTK_GPHY_LED_RX_BLINK_SET)
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#define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
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MTK_GPHY_LED_TX_BLINK_SET)
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#define MTK_PHY_LED_STATE_FORCE_ON 0
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#define MTK_PHY_LED_STATE_FORCE_BLINK 1
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#define MTK_PHY_LED_STATE_NETDEV 2
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void mtk_phy_select_page(struct phy_device *phydev, int page);
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void mtk_phy_restore_page(struct phy_device *phydev);
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u32 mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr);
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void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 mask, u32 set);
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void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 mask, u32 set);
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void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 set);
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void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 clr);
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#endif /* _MTK_EPHY_H_ */
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