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8e1fafb807
Add support for STM32MP25 SoC. Identification and hardware configuration registers allow to read the timer version and capabilities (counter width, ...). So, rework the probe to avoid touching ARR register by simply read the counter width when available. This may avoid messing with a possibly running timer. Also add useful bit fields to stm32-timers header file. Signed-off-by: Cheick Traore <cheick.traore@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
115 lines
2.8 KiB
C
115 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
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* Author: Cheick Traore <cheick.traore@foss.st.com>
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*
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* Originally based on the Linux kernel v6.1 drivers/mfd/stm32-timers.c.
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*/
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/timers.h>
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#include <dm/device_compat.h>
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#include <linux/bitfield.h>
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static void stm32_timers_get_arr_size(struct udevice *dev)
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{
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struct stm32_timers_plat *plat = dev_get_plat(dev);
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struct stm32_timers_priv *priv = dev_get_priv(dev);
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u32 arr;
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/* Backup ARR to restore it after getting the maximum value */
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arr = readl(plat->base + TIM_ARR);
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/*
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* Only the available bits will be written so when readback
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* we get the maximum value of auto reload register
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*/
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writel(~0L, plat->base + TIM_ARR);
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priv->max_arr = readl(plat->base + TIM_ARR);
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writel(arr, plat->base + TIM_ARR);
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}
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static int stm32_timers_probe_hwcfgr(struct udevice *dev)
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{
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struct stm32_timers_plat *plat = dev_get_plat(dev);
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struct stm32_timers_priv *priv = dev_get_priv(dev);
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u32 val;
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if (!plat->ipidr) {
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/* fallback to legacy method for probing counter width */
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stm32_timers_get_arr_size(dev);
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return 0;
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}
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val = readl(plat->base + TIM_IPIDR);
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/* Sanity check on IP identification register */
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if (val != plat->ipidr) {
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dev_err(dev, "Unexpected identification: %u\n", val);
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return -EINVAL;
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}
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val = readl(plat->base + TIM_HWCFGR2);
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/* Counter width in bits, max reload value is BIT(width) - 1 */
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priv->max_arr = BIT(FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val)) - 1;
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dev_dbg(dev, "TIM width: %ld\n", FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val));
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return 0;
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}
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static int stm32_timers_of_to_plat(struct udevice *dev)
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{
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struct stm32_timers_plat *plat = dev_get_plat(dev);
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plat->base = dev_read_addr_ptr(dev);
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if (!plat->base) {
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dev_err(dev, "can't get address\n");
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return -ENOENT;
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}
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plat->ipidr = (u32)dev_get_driver_data(dev);
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return 0;
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}
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static int stm32_timers_probe(struct udevice *dev)
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{
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struct stm32_timers_priv *priv = dev_get_priv(dev);
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struct clk clk;
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int ret = 0;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "failed to enable clock: ret=%d\n", ret);
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return ret;
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}
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priv->rate = clk_get_rate(&clk);
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ret = stm32_timers_probe_hwcfgr(dev);
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if (ret)
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clk_disable(&clk);
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return ret;
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}
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static const struct udevice_id stm32_timers_ids[] = {
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{ .compatible = "st,stm32-timers" },
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{ .compatible = "st,stm32mp25-timers", .data = STM32MP25_TIM_IPIDR },
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{}
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};
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U_BOOT_DRIVER(stm32_timers) = {
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.name = "stm32_timers",
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.id = UCLASS_NOP,
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.of_match = stm32_timers_ids,
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.of_to_plat = stm32_timers_of_to_plat,
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.plat_auto = sizeof(struct stm32_timers_plat),
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.probe = stm32_timers_probe,
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.priv_auto = sizeof(struct stm32_timers_priv),
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.bind = dm_scan_fdt_dev,
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};
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