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8e1fafb807
Add support for STM32MP25 SoC. Identification and hardware configuration registers allow to read the timer version and capabilities (counter width, ...). So, rework the probe to avoid touching ARR register by simply read the counter width when available. This may avoid messing with a possibly running timer. Also add useful bit fields to stm32-timers header file. Signed-off-by: Cheick Traore <cheick.traore@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
65 lines
2.3 KiB
C
65 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
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* Author: Cheick Traore <cheick.traore@foss.st.com>
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*
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* Originally based on the Linux kernel v6.1 include/linux/mfd/stm32-timers.h.
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*/
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#ifndef __STM32_TIMERS_H
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#define __STM32_TIMERS_H
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#include <clk.h>
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#define TIM_CR1 0x00 /* Control Register 1 */
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#define TIM_CR2 0x04 /* Control Register 2 */
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#define TIM_SMCR 0x08 /* Slave mode control reg */
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#define TIM_DIER 0x0C /* DMA/interrupt register */
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#define TIM_SR 0x10 /* Status register */
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#define TIM_EGR 0x14 /* Event Generation Reg */
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#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
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#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
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#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
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#define TIM_CNT 0x24 /* Counter */
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#define TIM_PSC 0x28 /* Prescaler */
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#define TIM_ARR 0x2c /* Auto-Reload Register */
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#define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */
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#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
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#define TIM_DCR 0x48 /* DMA control register */
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#define TIM_DMAR 0x4C /* DMA register for transfer */
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#define TIM_TISEL 0x68 /* Input Selection */
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#define TIM_HWCFGR2 0x3EC /* hardware configuration 2 Reg (MP25) */
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#define TIM_HWCFGR1 0x3F0 /* hardware configuration 1 Reg (MP25) */
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#define TIM_IPIDR 0x3F8 /* IP identification Reg (MP25) */
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#define TIM_CR1_CEN BIT(0) /* Counter Enable */
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#define TIM_CR1_ARPE BIT(7)
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#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
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#define TIM_CCER_CC1E BIT(0)
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#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
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#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
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#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
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#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
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#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
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#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
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#define TIM_EGR_UG BIT(0) /* Update Generation */
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#define TIM_HWCFGR2_CNT_WIDTH GENMASK(15, 8) /* Counter width */
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#define TIM_HWCFGR1_NB_OF_DT GENMASK(7, 4) /* Complementary outputs & dead-time generators */
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#define MAX_TIM_PSC 0xFFFF
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#define STM32MP25_TIM_IPIDR 0x00120002
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struct stm32_timers_plat {
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void __iomem *base;
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u32 ipidr;
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};
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struct stm32_timers_priv {
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u32 max_arr;
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ulong rate;
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};
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#endif
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