Yu Chien Peter Lin bc35b49a5c riscv: andes_plicsw: Fix IPI during OpenSBI invocation ...

On some AE350 boards, we need to explicitly initialize the priority
registers to a non-zero value so the boot hart can instruct secondary
harts to jump to OpenSBI.

This patch also updates the information about PLICSW.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

2023-07-06 17:28:08 +08:00

..

cpu

riscv: Fix alignment of RELA sections in the linker scripts

2023-06-27 10:09:51 +08:00

dts

riscv: dts: sync mpfs-icicle devicetree with linux

2023-07-06 17:28:08 +08:00

include/asm

riscv: define test_and_{set,clear}_bit in asm/bitops.h

2023-07-06 17:28:08 +08:00

lib

riscv: andes_plicsw: Fix IPI during OpenSBI invocation

2023-07-06 17:28:08 +08:00

config.mk

riscv: Support CONFIG_REMAKE_ELF

2023-04-20 20:45:08 +08:00

Kconfig

board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig

2023-04-20 16:08:45 +08:00

Makefile

riscv: support building double-float modules

2022-10-20 15:22:21 +08:00