mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-10-27 06:21:25 +01:00
62e92077a8
When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
91 lines
1.7 KiB
C
91 lines
1.7 KiB
C
/*
|
|
* (C) Copyright 2011
|
|
* Ilya Yanok, EmCraft Systems
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
#include <linux/types.h>
|
|
#include <common.h>
|
|
|
|
#ifndef CONFIG_SYS_DCACHE_OFF
|
|
|
|
#ifndef CONFIG_SYS_CACHELINE_SIZE
|
|
#define CONFIG_SYS_CACHELINE_SIZE 32
|
|
#endif
|
|
|
|
void invalidate_dcache_all(void)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
|
|
}
|
|
|
|
void flush_dcache_all(void)
|
|
{
|
|
asm volatile(
|
|
"0:"
|
|
"mrc p15, 0, r15, c7, c14, 3\n"
|
|
"bne 0b\n"
|
|
"mcr p15, 0, %0, c7, c10, 4\n"
|
|
: : "r"(0) : "memory"
|
|
);
|
|
}
|
|
|
|
static int check_cache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
int ok = 1;
|
|
|
|
if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
|
|
ok = 0;
|
|
|
|
if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
|
|
ok = 0;
|
|
|
|
if (!ok)
|
|
debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
|
|
start, stop);
|
|
|
|
return ok;
|
|
}
|
|
|
|
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
if (!check_cache_range(start, stop))
|
|
return;
|
|
|
|
while (start < stop) {
|
|
asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
|
|
start += CONFIG_SYS_CACHELINE_SIZE;
|
|
}
|
|
}
|
|
|
|
void flush_dcache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
if (!check_cache_range(start, stop))
|
|
return;
|
|
|
|
while (start < stop) {
|
|
asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
|
|
start += CONFIG_SYS_CACHELINE_SIZE;
|
|
}
|
|
|
|
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
|
|
}
|
|
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
|
|
void invalidate_dcache_all(void)
|
|
{
|
|
}
|
|
|
|
void flush_dcache_all(void)
|
|
{
|
|
}
|
|
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
|
|
|
|
/*
|
|
* Stub implementations for l2 cache operations
|
|
*/
|
|
|
|
__weak void l2_cache_disable(void) {}
|
|
|
|
#if defined CONFIG_SYS_THUMB_BUILD
|
|
__weak void invalidate_l2_cache(void) {}
|
|
#endif
|