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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
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*
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*/
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#ifndef mcf5307_h
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#define mcf5307_h
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/*
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* Size of internal RAM (RAMBAR)
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*/
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#define INT_RAM_SIZE 4096
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/* Bit definitions and macros for SYPCR */
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#define SYPCR_SWTAVAL 0x02
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#define SYPCR_SWTA 0x04
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#define SYPCR_SWT(x) ((x&0x3)<<3)
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#define SYPCR_SWP 0x20
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#define SYPCR_SWRI 0x40
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#define SYPCR_SWE 0x80
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/* Bit definitions and macros for CSMR */
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#define CSMR_V 0x01
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#define CSMR_UD 0x02
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#define CSMR_UC 0x04
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#define CSMR_SD 0x08
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#define CSMR_SC 0x10
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#define CSMR_CI 0x20
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#define CSMR_AM 0x40
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#define CSMR_WP 0x100
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/* Bit definitions and macros for DACR (SDRAM) */
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#define DACR_PM_CONTINUOUS 0x04
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#define DACR_IP_PRECHG_ALL 0x08
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#define DACR_PORT_SZ_32 0
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#define DACR_PORT_SZ_8 (1<<4)
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#define DACR_PORT_SZ_16 (2<<4)
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#define DACR_IMRS_INIT_CMD (1<<6)
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#define DACR_CMD_PIN(x) ((x&7)<<8)
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#define DACR_CASL(x) ((x&3)<<12)
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#define DACR_RE (1<<15)
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/* Bit definitions and macros for CSCR */
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#define CSCR_BSTW 0x08
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#define CSCR_BSTR 0x10
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#define CSCR_BEM 0x20
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#define CSCR_PS(x) ((x&0x3)<<6)
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#define CSCR_AA 0x100
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#define CSCR_WS ((x&0xf)<<10)
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/* Bit definitions for the ICR family of registers */
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#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
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#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
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#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
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#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
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#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
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#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
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#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
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#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
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#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
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#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
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#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
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#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
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#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
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#endif /* mcf5307_h */
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