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69f9c8bab8
Add OCRAM size macro for Gen5 and Arria 10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
53 lines
2.0 KiB
C
53 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
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*/
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#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
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#define _SOCFPGA_A10_BASE_HARDWARE_H_
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#define SOCFPGA_EMAC0_ADDRESS 0xff800000
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#define SOCFPGA_EMAC1_ADDRESS 0xff802000
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#define SOCFPGA_EMAC2_ADDRESS 0xff804000
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#define SOCFPGA_SDMMC_ADDRESS 0xff808000
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#define SOCFPGA_QSPIREGS_ADDRESS 0xff809000
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#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000
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#define SOCFPGA_UART1_ADDRESS 0xffc02100
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#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000
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#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400
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#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000
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#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
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#define SOCFPGA_SYSMGR_ADDRESS 0xffd06000
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#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000
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#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200
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#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300
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#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400
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#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
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#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
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#define SOCFPGA_MPUSCU_ADDRESS 0xffffc000
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#define SOCFPGA_MPUL2_ADDRESS 0xfffff000
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#define SOCFPGA_I2C0_ADDRESS 0xffc02200
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#define SOCFPGA_I2C1_ADDRESS 0xffc02300
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#define SOCFPGA_I2C2_ADDRESS 0xffc02400
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#define SOCFPGA_I2C3_ADDRESS 0xffc02500
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#define SOCFPGA_I2C4_ADDRESS 0xffc02600
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#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
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#define SOCFPGA_UART0_ADDRESS 0xffc02000
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#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
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#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
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#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
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#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
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#define SOCFPGA_SDR_ADDRESS 0xffcfb000
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#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000
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#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400
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#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
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#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300
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#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400
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#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500
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#define SOCFPGA_PHYS_OCRAM_SIZE 0x40000
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#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
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