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35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
70 lines
1.5 KiB
C
70 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/wdt.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
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void reset_cpu(void)
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{
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/* Enable watchdog clock */
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setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
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/* Reset pulse length is 13005 peripheral clock frames */
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writel(13000, &wdt->pulse);
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/* Force WDOG_RESET2 and RESOUT_N signal active */
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writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
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&wdt->mctrl);
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while (1)
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/* NOP */;
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}
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#if defined(CONFIG_ARCH_CPU_INIT)
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int arch_cpu_init(void)
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{
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/*
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* It might be necessary to flush data cache, if U-Boot is loaded
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* from kickstart bootloader, e.g. from S1L loader
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*/
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flush_dcache_all();
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return 0;
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}
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#else
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#error "You have to select CONFIG_ARCH_CPU_INIT"
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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printf("CPU: NXP LPC32XX\n");
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printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
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printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
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printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
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return 0;
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}
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#endif
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#ifdef CONFIG_LPC32XX_ETH
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int cpu_eth_init(struct bd_info *bis)
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{
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lpc32xx_eth_initialize(bis);
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return 0;
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}
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#endif
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