Thomas Skibo c0ffc12a70 riscv: Enable SPI flash env for SiFive Unmatched. ...

Enable saving environment to SPI flash memory on SiFive
Unmatched.

Signed-off-by: Thomas Skibo <thomas-git@skibo.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

2021-12-02 16:43:56 +08:00

..

ax25

riscv: ae350: enable Coherence Manager for ae350

2021-10-07 16:08:23 +08:00

fu540

board: sifive: use ccache driver instead of helper function

2021-09-07 10:34:29 +08:00

fu740

riscv: Enable SPI flash env for SiFive Unmatched.

2021-12-02 16:43:56 +08:00

generic

riscv: qemu: Switch to use binman to generate u-boot.itb

2021-05-19 17:01:51 +08:00

cpu.c

riscv: Remove OF_PRIOR_STAGE from RISC-V boards

2021-10-18 13:19:50 -04:00

Makefile

riscv: Move trap handler codes to mtrap.S

2018-12-18 09:56:27 +08:00

mtrap.S

riscv: Add option to print registers on exception

2020-02-10 14:51:08 +08:00

start.S

riscv: Remove OF_PRIOR_STAGE from RISC-V boards

2021-10-18 13:19:50 -04:00

u-boot-spl.lds

riscv: Add _image_binary_end for SPL

2020-06-04 09:44:08 +08:00

u-boot.lds

riscv: Fix breakage caused by linker relaxation

2020-02-10 14:50:53 +08:00