Anup Patel
e2842496ac
drivers: serial: Add SiFive UART driver
...
This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 09:56:54 +08:00
..
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-05-07 09:34:12 -04:00
2018-12-18 09:56:54 +08:00
2018-05-07 09:34:12 -04:00
2018-12-18 09:56:54 +08:00
2018-05-07 09:34:12 -04:00
2018-12-12 12:14:23 -05:00
2018-12-05 06:08:31 -07:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-12-07 08:13:46 -05:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-05-07 09:34:12 -04:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-12-03 10:44:10 -05:00
2018-05-26 18:19:17 -04:00
2018-11-28 23:04:53 -05:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-05-07 09:34:12 -04:00
2018-05-07 09:34:12 -04:00
2018-12-07 08:13:49 -05:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-05-07 09:34:12 -04:00
2018-11-14 09:16:28 -08:00
2018-05-07 09:34:12 -04:00
2018-05-07 09:34:12 -04:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-01-24 23:27:21 +01:00
2018-12-18 09:56:54 +08:00
2018-11-14 09:16:28 -08:00
2018-12-15 11:49:56 -05:00
2018-09-30 13:00:35 -04:00
2018-06-23 01:28:15 +09:00
2018-11-14 09:16:28 -08:00
2018-11-14 09:16:28 -08:00
2018-12-05 06:08:31 -07:00
2018-12-03 10:44:10 -05:00
2018-05-07 09:34:12 -04:00
2018-05-07 09:34:12 -04:00