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da3363d5d2
Add a driver for the broadwell northbridge. This sets up the location of several blocks of registers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/*
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* Copyright (C) 2011 The Chromium Authors
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/pch.h>
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static int broadwell_northbridge_early_init(struct udevice *dev)
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{
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/* Move earlier? */
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dm_pci_write_config32(dev, PCIEXBAR + 4, 0);
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/* 64MiB - 0-63 buses */
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dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1);
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dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
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dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1);
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dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1);
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writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR);
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writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR);
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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dm_pci_write_config8(dev, PAM0, 0x30);
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dm_pci_write_config8(dev, PAM1, 0x33);
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dm_pci_write_config8(dev, PAM2, 0x33);
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dm_pci_write_config8(dev, PAM3, 0x33);
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dm_pci_write_config8(dev, PAM4, 0x33);
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dm_pci_write_config8(dev, PAM5, 0x33);
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dm_pci_write_config8(dev, PAM6, 0x33);
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/* Device enable: IGD and Mini-HD */
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dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
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return 0;
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}
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static int broadwell_northbridge_probe(struct udevice *dev)
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{
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if (!(gd->flags & GD_FLG_RELOC))
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return broadwell_northbridge_early_init(dev);
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return 0;
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}
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static const struct udevice_id broadwell_northbridge_ids[] = {
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{ .compatible = "intel,broadwell-northbridge" },
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{ }
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};
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U_BOOT_DRIVER(broadwell_northbridge_drv) = {
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.name = "broadwell_northbridge",
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.id = UCLASS_NORTHBRIDGE,
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.of_match = broadwell_northbridge_ids,
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.probe = broadwell_northbridge_probe,
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};
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