Jonas Karlman 6da8400d7a clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.

Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.

Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
..
2023-07-13 11:29:40 +02:00
2022-07-08 17:57:33 -04:00
2022-09-02 13:40:42 -04:00
2021-09-24 14:30:46 -04:00
2022-02-23 05:25:17 +01:00
2020-01-24 11:19:52 -05:00
2022-03-02 13:59:29 -05:00
2022-01-19 18:11:34 +01:00
2023-01-31 15:46:39 +01:00
2022-03-02 13:59:29 -05:00
2022-04-01 16:56:53 -04:00
2023-05-31 14:05:34 -04:00
2021-09-30 08:08:56 -04:00