Patrice Chotard 1543bf794f clk: clk_stm32f7: fix PLL clock division factor
Fix clock division factor initialization for RCC_PLLCFGR
registers.

PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-17 07:44:13 -05:00
..
2017-06-01 07:03:01 -06:00
2017-06-01 07:03:01 -06:00