Xingyu Wu
005f9627d0
riscv: dts: jh7110: Add PLL clock controller node
Add child node about PLL clock controller in sys_syscon node.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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