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https://source.denx.de/u-boot/u-boot.git
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3ba9b1f7bd
Since turning from old build flow. New Altera SoCFPGA requires converting handsoff conversion via the python script. This is from official provided, and now sync to U-Boot with better location at tools/cv_xxxx. Meantime, requirement.txt is also provided to further explain the libraries require for these scripts. Signed-off-by: Brian Sune <briansune@gmail.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
197 lines
8.2 KiB
Python
Executable File
197 lines
8.2 KiB
Python
Executable File
# SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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"""
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Document renderer class for preloader source files
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Each document renderer takes care of a full construction of
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a specific file format using the required data model.
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Copyright (C) 2022 Intel Corporation <www.intel.com>
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Author: Lee, Kah Jing <kah.jing.lee@intel.com>
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"""
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import collections
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import doc
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class pll_config_h:
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"""
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pll_config.h renderer.
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"""
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def __init__(self, hpsModel, emifModel):
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""" renderer initialization """
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self.hpsModel = hpsModel
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self.emifModel = emifModel
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self.doc = doc.generated_c_source("__SOCFPGA_PLL_CONFIG_H__")
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def createContent(self):
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""" add the content based on settings parsed. eventually it will be
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written to pll_config.h file
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"""
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doc.c_source.line(self.doc)
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id = "CFG_HPS_DBCTRL_STAYOSC1"
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valueString = self.hpsModel.getSystemConfig("dbctrl_stayosc1")
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# Unfortunately hps.xml never tells us the data type of values
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# attributes. Here we workaround this type of problem, often
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# this is case-by-case, i.e. having to know which parameter that
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# we're dealing with, hence this ugly parameter-specific
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# if-statement needs here to workaround the data type inconsistency
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if valueString.lower() == "true":
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value = "1"
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else:
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value = "0"
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doc.c_source.define(self.doc, id, value )
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doc.c_source.line(self.doc)
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self.addMainPllSettings()
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doc.c_source.line(self.doc)
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self.addPeriphPllSettings()
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doc.c_source.line(self.doc)
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self.addSdramPllSettings()
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doc.c_source.line(self.doc)
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self.addClockFreq()
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doc.c_source.line(self.doc)
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self.addAlteraSettings()
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doc.c_source.line(self.doc)
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def addMainPllSettings(self):
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""" add pll settings to the file """
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paramMap = collections.OrderedDict()
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paramMap["VCO_DENOM"] = "main_pll_n"
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paramMap["VCO_NUMER"] = "main_pll_m"
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for key in paramMap.keys():
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id = "CFG_HPS_MAINPLLGRP_" + key
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value = self.hpsModel.getSystemConfig(paramMap[key])
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doc.c_source.define(self.doc, id, value )
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# main_pll_c0, main_pll_c1, main_pll_c2 are fixed counters,
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doc.c_source.define(self.doc, "CFG_HPS_MAINPLLGRP_MPUCLK_CNT", "0")
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doc.c_source.define(self.doc, "CFG_HPS_MAINPLLGRP_MAINCLK_CNT", "0")
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doc.c_source.define(self.doc, "CFG_HPS_MAINPLLGRP_DBGATCLK_CNT", "0")
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paramMap = collections.OrderedDict()
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paramMap["MAINQSPICLK_CNT"] = "main_pll_c3"
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paramMap["MAINNANDSDMMCCLK_CNT"] = "main_pll_c4"
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paramMap["CFGS2FUSER0CLK_CNT"] = "main_pll_c5"
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paramMap["MAINDIV_L3MPCLK"] = "l3_mp_clk_div"
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paramMap["MAINDIV_L3SPCLK"] = "l3_sp_clk_div"
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paramMap["MAINDIV_L4MPCLK"] = "l4_mp_clk_div"
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paramMap["MAINDIV_L4SPCLK"] = "l4_sp_clk_div"
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paramMap["DBGDIV_DBGATCLK"] = "dbg_at_clk_div"
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paramMap["DBGDIV_DBGCLK"] = "dbg_clk_div"
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paramMap["TRACEDIV_TRACECLK"] = "dbg_trace_clk_div"
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paramMap["L4SRC_L4MP"] = "l4_mp_clk_source"
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paramMap["L4SRC_L4SP"] = "l4_sp_clk_source"
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for key in paramMap.keys():
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id = "CFG_HPS_MAINPLLGRP_" + key
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value = self.hpsModel.getSystemConfig(paramMap[key])
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doc.c_source.define(self.doc, id, value )
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def addPeriphPllSettings(self):
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""" add peripheral pll settings to the file """
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paramMap = collections.OrderedDict()
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paramMap["VCO_DENOM"] = "periph_pll_n"
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paramMap["VCO_NUMER"] = "periph_pll_m"
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paramMap["VCO_PSRC"] = "periph_pll_source"
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paramMap["EMAC0CLK_CNT"] = "periph_pll_c0"
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paramMap["EMAC1CLK_CNT"] = "periph_pll_c1"
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paramMap["PERQSPICLK_CNT"] = "periph_pll_c2"
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paramMap["PERNANDSDMMCCLK_CNT"] = "periph_pll_c3"
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paramMap["PERBASECLK_CNT"] = "periph_pll_c4"
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paramMap["S2FUSER1CLK_CNT"] = "periph_pll_c5"
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paramMap["DIV_USBCLK"] = "usb_mp_clk_div"
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paramMap["DIV_SPIMCLK"] = "spi_m_clk_div"
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paramMap["DIV_CAN0CLK"] = "can0_clk_div"
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paramMap["DIV_CAN1CLK"] = "can1_clk_div"
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paramMap["GPIODIV_GPIODBCLK"] = "gpio_db_clk_div"
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paramMap["SRC_SDMMC"] = "sdmmc_clk_source"
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paramMap["SRC_NAND"] = "nand_clk_source"
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paramMap["SRC_QSPI"] = "qspi_clk_source"
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for key in paramMap.keys():
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id = "CFG_HPS_PERPLLGRP_" + key
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value = self.hpsModel.getSystemConfig(paramMap[key])
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doc.c_source.define(self.doc, id, value )
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def addSdramPllSettings(self):
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""" add sdram pll settings to the file """
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value = self.emifModel.getPllDefine("PLL_MEM_CLK_DIV")
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_VCO_DENOM", value )
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value = self.emifModel.getPllDefine("PLL_MEM_CLK_MULT")
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_VCO_NUMER", value )
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_VCO_SSRC", "0")
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT", "1")
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value = self.emifModel.getPllDefine("PLL_MEM_CLK_PHASE_DEG")
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE", value )
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT", "0")
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE", "0")
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT", "1")
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value = self.emifModel.getPllDefine("PLL_WRITE_CLK_PHASE_DEG")
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE", value )
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try:
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value = self.hpsModel.getSystemConfig("sdram_pll_c5")
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except ValueError:
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value = "5"
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT", value )
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doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE", "0")
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def addClockFreq(self):
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""" add clock frequency settings to the file """
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paramMap = collections.OrderedDict()
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paramMap["OSC1"] = "eosc1_clk_hz"
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paramMap["OSC2"] = "eosc2_clk_hz"
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paramMap["F2S_SDR_REF"] = "F2SCLK_SDRAMCLK_FREQ"
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paramMap["F2S_PER_REF"] = "F2SCLK_PERIPHCLK_FREQ"
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paramMap["MAINVCO"] = "main_pll_vco_hz"
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paramMap["PERVCO"] = "periph_pll_vco_hz"
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for key in paramMap.keys():
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id = "CFG_HPS_CLK_" + key + "_HZ"
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value = self.hpsModel.getSystemConfig(paramMap[key])
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doc.c_source.define(self.doc, id, value )
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eosc1 = int(self.hpsModel.getSystemConfig("eosc1_clk_hz"))
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eosc2 = int(self.hpsModel.getSystemConfig("eosc2_clk_hz"))
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m = int(self.emifModel.getPllDefine("PLL_MEM_CLK_MULT"))
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n = int(self.emifModel.getPllDefine("PLL_MEM_CLK_DIV"))
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vco = int(round(eosc1 * (m + 1) / (n + 1)))
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doc.c_source.define(self.doc, "CFG_HPS_CLK_SDRVCO_HZ", str(vco) )
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paramMap = collections.OrderedDict()
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paramMap["EMAC0"] = "emac0_clk_hz"
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paramMap["EMAC1"] = "emac1_clk_hz"
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paramMap["USBCLK"] = "usb_mp_clk_hz"
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paramMap["NAND"] = "nand_clk_hz"
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paramMap["SDMMC"] = "sdmmc_clk_hz"
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paramMap["QSPI"] = "qspi_clk_hz"
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paramMap["SPIM"] = "spi_m_clk_hz"
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paramMap["CAN0"] = "can0_clk_hz"
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paramMap["CAN1"] = "can1_clk_hz"
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paramMap["GPIODB"] = "gpio_db_clk_hz"
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paramMap["L4_MP"] = "l4_mp_clk_hz"
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paramMap["L4_SP"] = "l4_sp_clk_hz"
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for key in paramMap.keys():
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id = "CFG_HPS_CLK_" + key + "_HZ"
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value = self.hpsModel.getSystemConfig(paramMap[key])
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doc.c_source.define(self.doc, id, value )
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def addAlteraSettings(self):
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""" add Altera-related settings to the file """
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paramMap = collections.OrderedDict()
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paramMap["MPUCLK"] = "main_pll_c0_internal"
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paramMap["MAINCLK"] = "main_pll_c1_internal"
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paramMap["DBGATCLK"] = "main_pll_c2_internal"
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for key in paramMap.keys():
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id = "CFG_HPS_ALTERAGRP_" + key
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value = self.hpsModel.getSystemConfig(paramMap[key])
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doc.c_source.define(self.doc, id, value )
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def __str__(self):
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""" convert to string """
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self.createContent()
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return str(self.doc)
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