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24b0e2604e
Some macros are shared between host and gadget code, causing duplicated definitions. Move DWC2 macro definitions from host and gadget code into a common header to reduce duplication. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-6-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
59 lines
2.0 KiB
C
59 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*/
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#ifndef __DWC2_H__
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#define __DWC2_H__
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/* Host controller specific */
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#define DWC2_HC_PID_DATA0 0
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#define DWC2_HC_PID_DATA2 1
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#define DWC2_HC_PID_DATA1 2
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#define DWC2_HC_PID_MDATA 3
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#define DWC2_HC_PID_SETUP 3
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/* roothub.a masks */
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#define RH_A_NDP GENMASK(7, 0) /* number of downstream ports */
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#define RH_A_PSM BIT(8) /* power switching mode */
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#define RH_A_NPS BIT(9) /* no power switching */
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#define RH_A_DT BIT(10) /* device type (mbz) */
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#define RH_A_OCPM BIT(11) /* over current protection mode */
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#define RH_A_NOCP BIT(12) /* no over current protection */
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#define RH_A_POTPGT GENMASK(31, 24) /* power on to power good time */
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/* roothub.b masks */
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#define RH_B_DR 0x0000ffff /* device removable flags */
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#define RH_B_PPCM 0xffff0000 /* port power control mask */
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/* Default driver configuration */
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#define DWC2_DMA_ENABLE
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#define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */
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#undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */
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#define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */
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#define DWC2_MAX_CHANNELS 16 /* Max # of EPs */
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#define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS)
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#define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */
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#define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */
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#define DWC2_MAX_TRANSFER_SIZE 65535
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#define DWC2_MAX_PACKET_COUNT 511
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#define DWC2_PHY_TYPE_FS 0
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#define DWC2_PHY_TYPE_UTMI 1
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#define DWC2_PHY_TYPE_ULPI 2
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#define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
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#ifndef DWC2_UTMI_WIDTH
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#define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
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#endif
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#undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
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#define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */
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#undef DWC2_I2C_ENABLE /* Enable I2C */
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#undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */
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#undef DWC2_TS_DLINE /* External DLine pulsing */
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#undef DWC2_THR_CTL /* Threshold control */
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#define DWC2_TX_THR_LENGTH 64
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#undef DWC2_IC_USB_CAP /* IC Cap */
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#endif /* __DWC2_H__ */
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