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5eb14e1ea2
This patch ports the Cadence xSPI controller driver from
the Linux kernel. The controller supports three operating modes:
1. ACMD (Auto Command) mode
- Includes PIO and CDMA submodes.
- CDMA mode uses linked descriptors for high-performance,
low-overhead operation.
- PIO mode is suitable for simple, single-command transactions.
2. STIG (Software Triggered Instruction Generator) mode
- Issues low-level 128-bit instructions to memory.
- Uses the Slave DMA interface for data transfers.
3. Direct mode
- Enables direct data access through the slave interface
without commands.
Currently, only the STIG work mode is enabled. Additional modes will be
supported in future updates.
At the same time, also enabling the kconfig option for xSPI driver.
This driver has been ported and functionally verified on the Intel Simics
platform. It is intended for evaluation and experimental use at this stage.
Link: https://lore.kernel.org/all/1632038734-23999-1-git-send-email-pthombar@cadence.com/
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
227 lines
7.3 KiB
C
227 lines
7.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2025
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* Altera Corporation <www.altera.com>
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*/
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#ifndef __CADENCE_XSPI_H__
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#define __CADENCE_XSPI_H__
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#include <spi-mem.h>
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#include <reset.h>
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#include <linux/mtd/spi-nor.h>
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#include <linux/bitfield.h>
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#include <linux/log2.h>
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#define CDNS_XSPI_MAGIC_NUM_VALUE 0x6522
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#define CDNS_XSPI_MAX_BANKS 8
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#define CDNS_XSPI_NAME "cadence_xspi"
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/*
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* Note: below are additional auxiliary registers to
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* configure XSPI controller pin-strap settings
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*/
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/* PHY DQ timing register */
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#define CDNS_XSPI_CCP_PHY_DQ_TIMING 0x0000
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/* PHY DQS timing register */
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#define CDNS_XSPI_CCP_PHY_DQS_TIMING 0x0004
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/* PHY gate loopback control register */
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#define CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL 0x0008
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/* PHY DLL slave control register */
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#define CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL 0x0010
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/* DLL PHY control register */
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#define CDNS_XSPI_DLL_PHY_CTRL 0x1034
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/* Command registers */
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#define CDNS_XSPI_CMD_REG_0 0x0000
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#define CDNS_XSPI_CMD_REG_1 0x0004
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#define CDNS_XSPI_CMD_REG_2 0x0008
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#define CDNS_XSPI_CMD_REG_3 0x000C
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#define CDNS_XSPI_CMD_REG_4 0x0010
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#define CDNS_XSPI_CMD_REG_5 0x0014
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/* Command status registers */
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#define CDNS_XSPI_CMD_STATUS_REG 0x0044
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/* Controller status register */
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#define CDNS_XSPI_CTRL_STATUS_REG 0x0100
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#define CDNS_XSPI_INIT_COMPLETED BIT(16)
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#define CDNS_XSPI_INIT_LEGACY BIT(9)
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#define CDNS_XSPI_INIT_FAIL BIT(8)
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#define CDNS_XSPI_CTRL_BUSY BIT(7)
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/* Controller interrupt status register */
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#define CDNS_XSPI_INTR_STATUS_REG 0x0110
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#define CDNS_XSPI_STIG_DONE BIT(23)
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#define CDNS_XSPI_SDMA_ERROR BIT(22)
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#define CDNS_XSPI_SDMA_TRIGGER BIT(21)
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#define CDNS_XSPI_CMD_IGNRD_EN BIT(20)
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#define CDNS_XSPI_DDMA_TERR_EN BIT(18)
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#define CDNS_XSPI_CDMA_TREE_EN BIT(17)
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#define CDNS_XSPI_CTRL_IDLE_EN BIT(16)
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#define CDNS_XSPI_TRD_COMP_INTR_STATUS 0x0120
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#define CDNS_XSPI_TRD_ERR_INTR_STATUS 0x0130
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#define CDNS_XSPI_TRD_ERR_INTR_EN 0x0134
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/* Controller interrupt enable register */
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#define CDNS_XSPI_INTR_ENABLE_REG 0x0114
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#define CDNS_XSPI_INTR_EN BIT(31)
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#define CDNS_XSPI_STIG_DONE_EN BIT(23)
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#define CDNS_XSPI_SDMA_ERROR_EN BIT(22)
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#define CDNS_XSPI_SDMA_TRIGGER_EN BIT(21)
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#define CDNS_XSPI_INTR_MASK (CDNS_XSPI_INTR_EN | \
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CDNS_XSPI_STIG_DONE_EN | \
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CDNS_XSPI_SDMA_ERROR_EN | \
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CDNS_XSPI_SDMA_TRIGGER_EN)
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/* Controller config register */
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#define CDNS_XSPI_CTRL_CONFIG_REG 0x0230
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#define CDNS_XSPI_CTRL_WORK_MODE GENMASK(6, 5)
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#define CDNS_XSPI_WORK_MODE_DIRECT 0
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#define CDNS_XSPI_WORK_MODE_STIG 1
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#define CDNS_XSPI_WORK_MODE_ACMD 3
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/* SDMA trigger transaction registers */
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#define CDNS_XSPI_SDMA_SIZE_REG 0x0240
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#define CDNS_XSPI_SDMA_TRD_INFO_REG 0x0244
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#define CDNS_XSPI_SDMA_DIR BIT(8)
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/* Controller features register */
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#define CDNS_XSPI_CTRL_FEATURES_REG 0x0F04
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#define CDNS_XSPI_NUM_BANKS GENMASK(25, 24)
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#define CDNS_XSPI_DMA_DATA_WIDTH BIT(21)
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#define CDNS_XSPI_NUM_THREADS GENMASK(3, 0)
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/* Controller version register */
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#define CDNS_XSPI_CTRL_VERSION_REG 0x0F00
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#define CDNS_XSPI_MAGIC_NUM GENMASK(31, 16)
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#define CDNS_XSPI_CTRL_REV GENMASK(7, 0)
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/* STIG Profile 1.0 instruction fields (split into registers) */
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#define CDNS_XSPI_CMD_INSTR_TYPE GENMASK(6, 0)
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#define CDNS_XSPI_CMD_P1_R1_ADDR0 GENMASK(31, 24)
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#define CDNS_XSPI_CMD_P1_R2_ADDR1 GENMASK(7, 0)
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#define CDNS_XSPI_CMD_P1_R2_ADDR2 GENMASK(15, 8)
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#define CDNS_XSPI_CMD_P1_R2_ADDR3 GENMASK(23, 16)
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#define CDNS_XSPI_CMD_P1_R2_ADDR4 GENMASK(31, 24)
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#define CDNS_XSPI_CMD_P1_R3_ADDR5 GENMASK(7, 0)
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#define CDNS_XSPI_CMD_P1_R3_CMD GENMASK(23, 16)
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#define CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES GENMASK(30, 28)
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#define CDNS_XSPI_CMD_P1_R4_ADDR_IOS GENMASK(1, 0)
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#define CDNS_XSPI_CMD_P1_R4_CMD_IOS GENMASK(9, 8)
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#define CDNS_XSPI_CMD_P1_R4_BANK GENMASK(14, 12)
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/* STIG data sequence instruction fields (split into registers) */
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#define CDNS_XSPI_CMD_DSEQ_R2_DCNT_L GENMASK(31, 16)
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#define CDNS_XSPI_CMD_DSEQ_R3_DCNT_H GENMASK(15, 0)
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#define CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY GENMASK(25, 20)
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#define CDNS_XSPI_CMD_DSEQ_R4_BANK GENMASK(14, 12)
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#define CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS GENMASK(9, 8)
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#define CDNS_XSPI_CMD_DSEQ_R4_DIR BIT(4)
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/* STIG command status fields */
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#define CDNS_XSPI_CMD_STATUS_COMPLETED BIT(15)
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#define CDNS_XSPI_CMD_STATUS_FAILED BIT(14)
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#define CDNS_XSPI_CMD_STATUS_DQS_ERROR BIT(3)
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#define CDNS_XSPI_CMD_STATUS_CRC_ERROR BIT(2)
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#define CDNS_XSPI_CMD_STATUS_BUS_ERROR BIT(1)
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#define CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR BIT(0)
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#define CDNS_XSPI_STIG_DONE_FLAG BIT(0)
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#define CDNS_XSPI_TRD_STATUS 0x0104
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#define MODE_NO_OF_BYTES GENMASK(25, 24)
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#define MODEBYTES_COUNT 1
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/* Helper macros for filling command registers */
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#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase) ( \
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FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, (data_phase) ? \
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CDNS_XSPI_STIG_INSTR_TYPE_1 : CDNS_XSPI_STIG_INSTR_TYPE_0) | \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff))
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#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op) ( \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8) & 0xFF) | \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR2, ((op)->addr.val >> 16) & 0xFF) | \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR4, ((op)->addr.val >> 32) & 0xFF))
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#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, modebytes) ( \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R3_ADDR5, ((op)->addr.val >> 40) & 0xFF) | \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R3_CMD, (op)->cmd.opcode) | \
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FIELD_PREP(MODE_NO_OF_BYTES, modebytes) | \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES, (op)->addr.nbytes))
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#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, chipsel) ( \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R4_ADDR_IOS, ilog2((op)->addr.buswidth)) | \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R4_CMD_IOS, ilog2((op)->cmd.buswidth)) | \
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FIELD_PREP(CDNS_XSPI_CMD_P1_R4_BANK, chipsel))
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#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_1 \
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FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ)
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#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op) \
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FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R2_DCNT_L, (op)->data.nbytes & 0xFFFF)
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#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes) ( \
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FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \
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((op)->data.nbytes >> 16) & 0xffff) | \
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FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, \
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(op)->dummy.buswidth != 0 ? \
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(((dummybytes) * 8) / (op)->dummy.buswidth) : \
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0))
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#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \
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FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_BANK, chipsel) | \
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FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS, \
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ilog2((op)->data.buswidth)) | \
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FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DIR, \
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((op)->data.dir == SPI_MEM_DATA_IN) ? \
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CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE))
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enum cdns_xspi_stig_instr_type {
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CDNS_XSPI_STIG_INSTR_TYPE_0,
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CDNS_XSPI_STIG_INSTR_TYPE_1,
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CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ = 127,
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};
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enum cdns_xspi_sdma_dir {
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CDNS_XSPI_SDMA_DIR_READ,
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CDNS_XSPI_SDMA_DIR_WRITE,
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};
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enum cdns_xspi_stig_cmd_dir {
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CDNS_XSPI_STIG_CMD_DIR_READ,
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CDNS_XSPI_STIG_CMD_DIR_WRITE,
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};
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struct cdns_xspi_plat {
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struct device *dev;
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struct reset_ctl_bulk *resets;
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void __iomem *iobase;
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void __iomem *auxbase;
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void __iomem *sdmabase;
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int cur_cs;
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unsigned int sdmasize;
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bool sdma_error;
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void *in_buffer;
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const void *out_buffer;
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u8 hw_num_banks;
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void (*sdma_handler)(struct cdns_xspi_plat *cdns_xspi);
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void (*set_interrupts_handler)(struct cdns_xspi_plat *cdns_xspi, bool enabled);
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};
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#endif /* __CADENCE_XSPI_H__ */
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