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8a3c3a8a11
The Designware IP integrated in TH1520 SoC requires extra clock configuration to operate correctly. The Linux kernel's T-Head DWMAC glue driver is ported and adapted to U-Boot's API. Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
289 lines
6.9 KiB
C
289 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* T-HEAD DWMAC platform driver
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*
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* Copyright (C) 2021 Alibaba Group Holding Limited.
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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* Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
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*
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*/
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <linux/bitfield.h>
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#include <phy.h>
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#include "designware.h"
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#define GMAC_CLK_EN 0x00
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#define GMAC_TX_CLK_EN BIT(1)
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#define GMAC_TX_CLK_N_EN BIT(2)
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#define GMAC_TX_CLK_OUT_EN BIT(3)
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#define GMAC_RX_CLK_EN BIT(4)
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#define GMAC_RX_CLK_N_EN BIT(5)
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#define GMAC_EPHY_REF_CLK_EN BIT(6)
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#define GMAC_RXCLK_DELAY_CTRL 0x04
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#define GMAC_RXCLK_BYPASS BIT(15)
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#define GMAC_RXCLK_INVERT BIT(14)
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#define GMAC_RXCLK_DELAY GENMASK(4, 0)
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#define GMAC_TXCLK_DELAY_CTRL 0x08
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#define GMAC_TXCLK_BYPASS BIT(15)
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#define GMAC_TXCLK_INVERT BIT(14)
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#define GMAC_TXCLK_DELAY GENMASK(4, 0)
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#define GMAC_PLLCLK_DIV 0x0c
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#define GMAC_PLLCLK_DIV_EN BIT(31)
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#define GMAC_PLLCLK_DIV_NUM GENMASK(7, 0)
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#define GMAC_GTXCLK_SEL 0x18
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#define GMAC_GTXCLK_SEL_PLL BIT(0)
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#define GMAC_INTF_CTRL 0x1c
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#define PHY_INTF_MASK BIT(0)
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#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1)
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#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0)
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#define GMAC_TXCLK_OEN 0x20
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#define TXCLK_DIR_MASK BIT(0)
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#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0)
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#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1)
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#define GMAC_RGMII_CLK_RATE 125000000
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struct dwmac_thead_plat {
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struct dw_eth_pdata dw_eth_pdata;
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void __iomem *apb_base;
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};
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static int dwmac_thead_set_phy_if(struct dwmac_thead_plat *plat)
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{
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u32 phyif;
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switch (plat->dw_eth_pdata.eth_pdata.phy_interface) {
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case PHY_INTERFACE_MODE_MII:
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phyif = PHY_INTF_MII_GMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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phyif = PHY_INTF_RGMII;
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break;
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default:
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return -EINVAL;
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}
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writel(phyif, plat->apb_base + GMAC_INTF_CTRL);
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return 0;
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}
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static int dwmac_thead_set_txclk_dir(struct dwmac_thead_plat *plat)
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{
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u32 txclk_dir;
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switch (plat->dw_eth_pdata.eth_pdata.phy_interface) {
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case PHY_INTERFACE_MODE_MII:
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txclk_dir = TXCLK_DIR_INPUT;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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txclk_dir = TXCLK_DIR_OUTPUT;
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break;
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default:
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return -EINVAL;
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}
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writel(txclk_dir, plat->apb_base + GMAC_TXCLK_OEN);
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return 0;
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}
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static unsigned long dwmac_thead_rgmii_tx_rate(int speed)
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{
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switch (speed) {
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case 10:
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return 2500000;
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case 100:
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return 25000000;
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case 1000:
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return 125000000;
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}
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return -EINVAL;
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}
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static int dwmac_thead_set_clk_tx_rate(struct dwmac_thead_plat *plat,
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struct dw_eth_dev *edev,
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unsigned long tx_rate)
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{
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unsigned long rate;
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u32 div, reg;
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rate = clk_get_rate(&edev->clocks[0]);
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writel(0, plat->apb_base + GMAC_PLLCLK_DIV);
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div = rate / tx_rate;
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if (rate != tx_rate * div) {
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pr_err("invalid gmac rate %lu\n", rate);
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return -EINVAL;
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}
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reg = FIELD_PREP(GMAC_PLLCLK_DIV_EN, 1) |
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FIELD_PREP(GMAC_PLLCLK_DIV_NUM, div);
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writel(reg, plat->apb_base + GMAC_PLLCLK_DIV);
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return 0;
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}
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static int dwmac_thead_enable_clk(struct dwmac_thead_plat *plat)
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{
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u32 reg;
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switch (plat->dw_eth_pdata.eth_pdata.phy_interface) {
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case PHY_INTERFACE_MODE_MII:
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reg = GMAC_RX_CLK_EN | GMAC_TX_CLK_EN;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* use pll */
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writel(GMAC_GTXCLK_SEL_PLL, plat->apb_base + GMAC_GTXCLK_SEL);
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reg = GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN |
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GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN;
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break;
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default:
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return -EINVAL;
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}
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writel(reg, plat->apb_base + GMAC_CLK_EN);
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return 0;
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}
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static int dwmac_thead_eth_start(struct udevice *dev)
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{
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struct dwmac_thead_plat *plat = dev_get_plat(dev);
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struct dw_eth_dev *edev = dev_get_priv(dev);
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phy_interface_t interface;
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bool is_rgmii;
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long tx_rate;
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int ret;
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interface = plat->dw_eth_pdata.eth_pdata.phy_interface;
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is_rgmii = (interface == PHY_INTERFACE_MODE_RGMII) |
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(interface == PHY_INTERFACE_MODE_RGMII_ID) |
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(interface == PHY_INTERFACE_MODE_RGMII_RXID) |
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(interface == PHY_INTERFACE_MODE_RGMII_TXID);
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/*
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* When operating in RGMII mode, the TX clock is generated by an
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* internal divider and fed to the MAC. Configure and enable it before
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* initializing the MAC.
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*/
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if (is_rgmii) {
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ret = dwmac_thead_set_clk_tx_rate(plat, edev,
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GMAC_RGMII_CLK_RATE);
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if (ret)
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return ret;
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}
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ret = designware_eth_init(edev, plat->dw_eth_pdata.eth_pdata.enetaddr);
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if (ret)
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return ret;
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if (is_rgmii) {
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tx_rate = dwmac_thead_rgmii_tx_rate(edev->phydev->speed);
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if (tx_rate < 0)
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return tx_rate;
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ret = dwmac_thead_set_clk_tx_rate(plat, edev, tx_rate);
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if (ret)
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return ret;
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}
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ret = designware_eth_enable(edev);
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if (ret)
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return ret;
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return 0;
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}
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static int dwmac_thead_probe(struct udevice *dev)
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{
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struct dwmac_thead_plat *plat = dev_get_plat(dev);
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unsigned int reg;
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int ret;
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ret = designware_eth_probe(dev);
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if (ret)
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return ret;
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ret = dwmac_thead_set_phy_if(plat);
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if (ret) {
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pr_err("failed to set phy interface: %d\n", ret);
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return ret;
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}
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ret = dwmac_thead_set_txclk_dir(plat);
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if (ret) {
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pr_err("failed to set TX clock direction: %d\n", ret);
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return ret;
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}
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reg = readl(plat->apb_base + GMAC_RXCLK_DELAY_CTRL);
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reg &= ~(GMAC_RXCLK_DELAY);
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reg |= FIELD_PREP(GMAC_RXCLK_DELAY, 0);
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writel(reg, plat->apb_base + GMAC_RXCLK_DELAY_CTRL);
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reg = readl(plat->apb_base + GMAC_TXCLK_DELAY_CTRL);
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reg &= ~(GMAC_TXCLK_DELAY);
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reg |= FIELD_PREP(GMAC_TXCLK_DELAY, 0);
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writel(reg, plat->apb_base + GMAC_TXCLK_DELAY_CTRL);
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ret = dwmac_thead_enable_clk(plat);
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if (ret)
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pr_err("failed to enable clock: %d\n", ret);
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return ret;
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}
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static int dwmac_thead_of_to_plat(struct udevice *dev)
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{
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struct dwmac_thead_plat *pdata = dev_get_plat(dev);
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pdata->apb_base = dev_read_addr_index_ptr(dev, 1);
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if (!pdata->apb_base) {
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pr_err("failed to get apb registers\n");
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return -ENOENT;
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}
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return designware_eth_of_to_plat(dev);
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}
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static const struct eth_ops dwmac_thead_eth_ops = {
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.start = dwmac_thead_eth_start,
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.send = designware_eth_send,
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.recv = designware_eth_recv,
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.free_pkt = designware_eth_free_pkt,
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.stop = designware_eth_stop,
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.write_hwaddr = designware_eth_write_hwaddr,
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};
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static const struct udevice_id dwmac_thead_match[] = {
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{ .compatible = "thead,th1520-gmac" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(dwmac_thead) = {
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.name = "dwmac_thead",
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.id = UCLASS_ETH,
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.of_match = dwmac_thead_match,
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.of_to_plat = dwmac_thead_of_to_plat,
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.probe = dwmac_thead_probe,
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.ops = &dwmac_thead_eth_ops,
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.priv_auto = sizeof(struct dw_eth_dev),
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.plat_auto = sizeof(struct dwmac_thead_plat),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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