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ed0e33cec0
- Add support for configuring the PHY DLL master control register for all SD/eMMC timing modes (DS, HS, SDR, DDR, HS200, HS400) by extending the PHY configuration arrays and writing the value during PHY adjustment. - Fix tuning reliability by toggling the DLL reset before and after updating the PHY_DLL_SLAVE_CTRL_REG_ADDR register. Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com> Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
330 lines
10 KiB
C
330 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-platform_driver
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/*
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* Copyright (C) 2023 Starfive.
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* Author: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*/
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#include <dm.h>
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#include <asm/global_data.h>
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#include <dm/device_compat.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/sizes.h>
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#include <linux/libfdt.h>
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#include <mmc.h>
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#include <sdhci.h>
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#include "sdhci-cadence.h"
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/* IO Delay Information */
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#define SDHCI_CDNS_HRS07 0x1C
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#define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16)
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#define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0)
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/* PHY Control and Status */
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#define SDHCI_CDNS_HRS09 0x24
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#define SDHCI_CDNS_HRS09_RDDATA_EN BIT(16)
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#define SDHCI_CDNS_HRS09_RDCMD_EN BIT(15)
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#define SDHCI_CDNS_HRS09_EXTENDED_WR_MODE BIT(3)
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#define SDHCI_CDNS_HRS09_EXTENDED_RD_MODE BIT(2)
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#define SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE BIT(1)
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#define SDHCI_CDNS_HRS09_PHY_SW_RESET BIT(0)
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/* SDCLK adjustment */
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#define SDHCI_CDNS_HRS10 0x28
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#define SDHCI_CDNS_HRS10_HCSDCLKADJ GENMASK(19, 16)
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/* CMD/DAT output delay */
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#define SDHCI_CDNS_HRS16 0x40
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/* PHY Special Function Registers */
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/* register to control the DQ related timing */
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#define PHY_DQ_TIMING_REG_ADDR 0x2000
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/* register to control the DQS related timing */
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#define PHY_DQS_TIMING_REG_ADDR 0x2004
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/* register to control the gate and loopback control related timing */
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#define PHY_GATE_LPBK_CTRL_REG_ADDR 0x2008
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/* register to control the Master DLL logic */
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#define PHY_DLL_MASTER_CTRL_REG_ADDR 0x200C
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/* register to control the Slave DLL logic */
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#define PHY_DLL_SLAVE_CTRL_REG_ADDR 0x2010
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#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY GENMASK(31, 24)
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#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY GENMASK(7, 0)
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#define SDHCI_CDNS6_PHY_CFG_NUM 5
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#define SDHCI_CDNS6_CTRL_CFG_NUM 4
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struct sdhci_cdns6_phy_cfg {
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const char *property;
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u32 val;
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};
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struct sdhci_cdns6_ctrl_cfg {
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const char *property;
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u32 val;
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};
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static struct sdhci_cdns6_phy_cfg sd_ds_phy_cfgs[] = {
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{ "cdns,phy-dqs-timing-delay-sd-ds", 0x00380004, },
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{ "cdns,phy-gate-lpbk-ctrl-delay-sd-ds", 0x01A00040, },
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{ "cdns,phy-dll-slave-ctrl-sd-ds", 0x00000000, },
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{ "cdns,phy-dq-timing-delay-sd-ds", 0x00000001, },
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{ "cdns,phy-dll-master-ctrl-sd-ds", 0x00800004, },
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};
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static struct sdhci_cdns6_phy_cfg sd_hs_phy_cfgs[] = {
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{ "cdns,phy-dqs-timing-delay-sd-hs", 0x00380004, },
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{ "cdns,phy-gate-lpbk-ctrl-delay-sd-hs", 0x01A00040, },
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{ "cdns,phy-dll-slave-ctrl-sd-hs", 0x00000000, },
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{ "cdns,phy-dq-timing-delay-sd-hs", 0x00000001, },
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{ "cdns,phy-dll-master-ctrl-sd-hs", 0x00800004, },
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};
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static struct sdhci_cdns6_phy_cfg emmc_sdr_phy_cfgs[] = {
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{ "cdns,phy-dqs-timing-delay-emmc-sdr", 0x00380004, },
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{ "cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr", 0x01A00040, },
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{ "cdns,phy-dll-slave-ctrl-emmc-sdr", 0x00000000, },
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{ "cdns,phy-dq-timing-delay-emmc-sdr", 0x00000001, },
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{ "cdns,phy-dll-master-ctrl-emmc-sdr", 0x00800004, },
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};
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static struct sdhci_cdns6_phy_cfg emmc_ddr_phy_cfgs[] = {
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{ "cdns,phy-dqs-timing-delay-emmc-ddr", 0x00380004, },
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{ "cdns,phy-gate-lpbk-ctrl-delay-emmc-ddr", 0x01A00040, },
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{ "cdns,phy-dll-slave-ctrl-emmc-ddr", 0x00000000, },
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{ "cdns,phy-dq-timing-delay-emmc-ddr", 0x10000001, },
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{ "cdns,phy-dll-master-ctrl-emmc-ddr", 0x00800004, },
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};
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static struct sdhci_cdns6_phy_cfg emmc_hs200_phy_cfgs[] = {
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{ "cdns,phy-dqs-timing-delay-emmc-hs200", 0x00380004, },
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{ "cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200", 0x01A00040, },
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{ "cdns,phy-dll-slave-ctrl-emmc-hs200", 0x00DADA00, },
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{ "cdns,phy-dq-timing-delay-emmc-hs200", 0x00000001, },
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{ "cdns,phy-dll-master-ctrl-emmc-hs200", 0x00000004, },
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};
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static struct sdhci_cdns6_phy_cfg emmc_hs400_phy_cfgs[] = {
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{ "cdns,phy-dqs-timing-delay-emmc-hs400", 0x00280004, },
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{ "cdns,phy-gate-lpbk-ctrl-delay-emmc-hs400", 0x01A00040, },
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{ "cdns,phy-dll-slave-ctrl-emmc-hs400", 0x00DAD800, },
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{ "cdns,phy-dq-timing-delay-emmc-hs400", 0x00000001, },
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{ "cdns,phy-dll-master-ctrl-emmc-hs400", 0x00000004, },
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};
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static struct sdhci_cdns6_ctrl_cfg sd_ds_ctrl_cfgs[] = {
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{ "cdns,ctrl-hrs09-timing-delay-sd-ds", 0x0001800C, },
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{ "cdns,ctrl-hrs10-lpbk-ctrl-delay-sd-ds", 0x00020000, },
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{ "cdns,ctrl-hrs16-slave-ctrl-sd-ds", 0x00000000, },
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{ "cdns,ctrl-hrs07-timing-delay-sd-ds", 0x00080000, },
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};
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static struct sdhci_cdns6_ctrl_cfg sd_hs_ctrl_cfgs[] = {
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{ "cdns,ctrl-hrs09-timing-delay-sd-hs", 0x0001800C, },
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{ "cdns,ctrl-hrs10-lpbk-ctrl-delay-sd-hs", 0x00030000, },
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{ "cdns,ctrl-hrs16-slave-ctrl-sd-hs", 0x00000000, },
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{ "cdns,ctrl-hrs07-timing-delay-sd-hs", 0x00080000, },
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};
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static struct sdhci_cdns6_ctrl_cfg emmc_sdr_ctrl_cfgs[] = {
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{ "cdns,ctrl-hrs09-timing-delay-emmc-sdr", 0x0001800C, },
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{ "cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr", 0x00030000, },
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{ "cdns,ctrl-hrs16-slave-ctrl-emmc-sdr", 0x00000000, },
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{ "cdns,ctrl-hrs07-timing-delay-emmc-sdr", 0x00080000, },
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};
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static struct sdhci_cdns6_ctrl_cfg emmc_ddr_ctrl_cfgs[] = {
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{ "cdns,ctrl-hrs09-timing-delay-emmc-ddr", 0x0001800C, },
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{ "cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-ddr", 0x00020000, },
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{ "cdns,ctrl-hrs16-slave-ctrl-emmc-ddr", 0x11000001, },
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{ "cdns,ctrl-hrs07-timing-delay-emmc-ddr", 0x00090001, },
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};
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static struct sdhci_cdns6_ctrl_cfg emmc_hs200_ctrl_cfgs[] = {
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{ "cdns,ctrl-hrs09-timing-delay-emmc-hs200", 0x00018000, },
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{ "cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200", 0x00080000, },
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{ "cdns,ctrl-hrs16-slave-ctrl-emmc-hs200", 0x00000000, },
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{ "cdns,ctrl-hrs07-timing-delay-emmc-hs200", 0x00090000, },
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};
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static struct sdhci_cdns6_ctrl_cfg emmc_hs400_ctrl_cfgs[] = {
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{ "cdns,ctrl-hrs09-timing-delay-emmc-hs400", 0x00018000, },
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{ "cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs400", 0x00080000, },
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{ "cdns,ctrl-hrs16-slave-ctrl-emmc-hs400", 0x11000000, },
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{ "cdns,ctrl-hrs07-timing-delay-emmc-hs400", 0x00080000, },
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};
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static u32 sdhci_cdns6_read_phy_reg(struct sdhci_cdns_plat *plat, u32 addr)
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{
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writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04);
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return readl(plat->hrs_addr + SDHCI_CDNS_HRS05);
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}
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static void sdhci_cdns6_write_phy_reg(struct sdhci_cdns_plat *plat, u32 addr, u32 val)
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{
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writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04);
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writel(val, plat->hrs_addr + SDHCI_CDNS_HRS05);
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}
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static int sdhci_cdns6_reset_phy_dll(struct sdhci_cdns_plat *plat, bool reset)
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{
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void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS09;
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u32 tmp;
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int ret;
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tmp = readl(reg);
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tmp &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET;
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/* Switch On DLL Reset */
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if (reset)
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tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 0);
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else
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tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 1);
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writel(tmp, reg);
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/* After reset, wait until HRS09.PHY_INIT_COMPLETE is set to 1 within 3000us*/
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if (!reset) {
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ret = readl_poll_timeout(reg, tmp, (tmp & SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE),
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3000);
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}
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return ret;
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}
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int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode)
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{
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struct sdhci_cdns6_phy_cfg *sdhci_cdns6_phy_cfgs;
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struct sdhci_cdns6_ctrl_cfg *sdhci_cdns6_ctrl_cfgs;
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u32 tmp;
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int i, ret;
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switch (mode) {
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case UHS_SDR12:
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case MMC_LEGACY:
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sdhci_cdns6_phy_cfgs = sd_ds_phy_cfgs;
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sdhci_cdns6_ctrl_cfgs = sd_ds_ctrl_cfgs;
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break;
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case SD_HS:
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case UHS_SDR25:
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case MMC_HS:
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sdhci_cdns6_phy_cfgs = sd_hs_phy_cfgs;
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sdhci_cdns6_ctrl_cfgs = sd_hs_ctrl_cfgs;
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break;
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case UHS_SDR50:
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case MMC_HS_52:
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sdhci_cdns6_phy_cfgs = emmc_sdr_phy_cfgs;
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sdhci_cdns6_ctrl_cfgs = emmc_sdr_ctrl_cfgs;
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break;
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case UHS_DDR50:
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case MMC_DDR_52:
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sdhci_cdns6_phy_cfgs = emmc_ddr_phy_cfgs;
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sdhci_cdns6_ctrl_cfgs = emmc_ddr_ctrl_cfgs;
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break;
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case UHS_SDR104:
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case MMC_HS_200:
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sdhci_cdns6_phy_cfgs = emmc_hs200_phy_cfgs;
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sdhci_cdns6_ctrl_cfgs = emmc_hs200_ctrl_cfgs;
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break;
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case MMC_HS_400:
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case MMC_HS_400_ES:
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sdhci_cdns6_phy_cfgs = emmc_hs400_phy_cfgs;
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sdhci_cdns6_ctrl_cfgs = emmc_hs400_ctrl_cfgs;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < SDHCI_CDNS6_PHY_CFG_NUM; i++)
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dev_read_u32(dev, sdhci_cdns6_phy_cfgs[i].property, &sdhci_cdns6_phy_cfgs[i].val);
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for (i = 0; i < SDHCI_CDNS6_CTRL_CFG_NUM; i++)
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dev_read_u32(dev, sdhci_cdns6_ctrl_cfgs[i].property, &sdhci_cdns6_ctrl_cfgs[i].val);
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/* Switch On the DLL Reset */
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sdhci_cdns6_reset_phy_dll(plat, true);
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sdhci_cdns6_write_phy_reg(plat, PHY_DQS_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[0].val);
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sdhci_cdns6_write_phy_reg(plat, PHY_GATE_LPBK_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[1].val);
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sdhci_cdns6_write_phy_reg(plat, PHY_DLL_MASTER_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[4].val);
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sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[2].val);
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/* Switch Off the DLL Reset */
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ret = sdhci_cdns6_reset_phy_dll(plat, false);
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if (ret) {
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printf("sdhci_cdns6_reset_phy is not completed\n");
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return ret;
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}
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/* Set PHY DQ TIMING control register */
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sdhci_cdns6_write_phy_reg(plat, PHY_DQ_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[3].val);
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/* Set HRS09 register */
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tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS09);
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tmp &= ~(SDHCI_CDNS_HRS09_EXTENDED_WR_MODE |
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SDHCI_CDNS_HRS09_EXTENDED_RD_MODE |
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SDHCI_CDNS_HRS09_RDDATA_EN |
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SDHCI_CDNS_HRS09_RDCMD_EN);
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tmp |= sdhci_cdns6_ctrl_cfgs[0].val;
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writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS09);
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/* Set HRS10 register */
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tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS10);
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tmp &= ~SDHCI_CDNS_HRS10_HCSDCLKADJ;
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tmp |= sdhci_cdns6_ctrl_cfgs[1].val;
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writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS10);
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/* Set HRS16 register */
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writel(sdhci_cdns6_ctrl_cfgs[2].val, plat->hrs_addr + SDHCI_CDNS_HRS16);
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/* Set HRS07 register */
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writel(sdhci_cdns6_ctrl_cfgs[3].val, plat->hrs_addr + SDHCI_CDNS_HRS07);
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return 0;
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}
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int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat)
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{
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return sdhci_cdns6_phy_adj(dev, plat, MMC_LEGACY);
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}
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int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val)
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{
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u32 tmp, tuneval;
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int ret;
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tuneval = (val * 256) / SDHCI_CDNS_MAX_TUNING_LOOP;
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tmp = sdhci_cdns6_read_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR);
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tmp &= ~(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY |
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PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY);
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tmp |= FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY, tuneval) |
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FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY, tuneval);
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/* Switch On the DLL Reset */
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sdhci_cdns6_reset_phy_dll(plat, true);
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sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, tmp);
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/* Switch Off the DLL Reset */
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ret = sdhci_cdns6_reset_phy_dll(plat, false);
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if (ret) {
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printf("sdhci_cdns6_reset_phy is not completed\n");
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return ret;
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}
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return 0;
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}
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