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4146a31dce
Currently xilinx_pm_request API supports four u32 payloads. However the legacy SMC format supports five u32 request payloads and extended SMC format supports six u32 request payloads. Add support for the same in xilinx_pm_request API. Also add two dummy arguments to all the callers of xilinx_pm_request. The TF-A always fills seven u32 return payload so add support for the same in xilinx_pm_request API. Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
156 lines
3.3 KiB
C
156 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ZynqMP GPIO modepin driver
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*
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* Copyright (C) 2021 Xilinx, Inc.
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*/
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <dm.h>
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#include <asm/arch/hardware.h>
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#include <zynqmp_firmware.h>
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#define OUTEN(pin) (BIT(0) << (pin))
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#define INVAL(pin) (BIT(4) << (pin))
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#define OUTVAL(pin) (BIT(8) << (pin))
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#define ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK 0xF0F
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#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL (ZYNQMP_CRL_APB_BASEADDR + \
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(0x250U))
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static int get_gpio_modepin(u32 *ret_payload)
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{
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return xilinx_pm_request(PM_MMIO_READ, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
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0, 0, 0, 0, 0, ret_payload);
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}
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static int set_gpio_modepin(int val)
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{
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return xilinx_pm_request(PM_MMIO_WRITE, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
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ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK,
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val, 0, 0, 0, NULL);
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}
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static int modepin_gpio_direction_input(struct udevice *dev,
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unsigned int offset)
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{
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return 0;
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}
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static int modepin_gpio_set_value(struct udevice *dev, unsigned int offset,
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int value)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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u32 out_val = 0;
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int ret;
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ret = get_gpio_modepin(ret_payload);
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if (ret)
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return ret;
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if (value)
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out_val = OUTVAL(offset) | ret_payload[1];
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else
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out_val = ~OUTVAL(offset) & ret_payload[1];
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return set_gpio_modepin(out_val);
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}
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static int modepin_gpio_direction_output(struct udevice *dev,
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unsigned int offset, int value)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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u32 out_en = 0;
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int ret;
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ret = get_gpio_modepin(ret_payload);
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if (ret)
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return ret;
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if (value)
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out_en = OUTEN(offset) | ret_payload[1];
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else
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out_en = ~OUTEN(offset) & ret_payload[1];
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ret = set_gpio_modepin(out_en);
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if (ret)
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return ret;
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return modepin_gpio_set_value(dev, offset, value);
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}
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static int modepin_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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desc->offset = args->args[0];
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return 0;
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}
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static int modepin_gpio_get_value(struct udevice *dev, unsigned int offset)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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ret = get_gpio_modepin(ret_payload);
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if (ret)
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return ret;
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return (INVAL(offset) & ret_payload[1]) ? 1 : 0;
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}
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static int modepin_gpio_get_function(struct udevice *dev, unsigned int offset)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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ret = get_gpio_modepin(ret_payload);
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if (ret)
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return ret;
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return (OUTEN(offset) & ret_payload[1]) ? GPIOF_OUTPUT : GPIOF_INPUT;
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}
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static const struct dm_gpio_ops modepin_gpio_ops = {
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.direction_input = modepin_gpio_direction_input,
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.direction_output = modepin_gpio_direction_output,
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.get_value = modepin_gpio_get_value,
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.set_value = modepin_gpio_set_value,
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.get_function = modepin_gpio_get_function,
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.xlate = modepin_gpio_xlate,
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};
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static int modepin_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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const void *label_ptr;
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label_ptr = dev_read_prop(dev, "label", NULL);
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if (label_ptr) {
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uc_priv->bank_name = strdup(label_ptr);
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if (!uc_priv->bank_name)
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return -ENOMEM;
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} else {
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uc_priv->bank_name = dev->name;
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}
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uc_priv->gpio_count = 4;
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return 0;
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}
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static const struct udevice_id modepin_gpio_ids[] = {
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{ .compatible = "xlnx,zynqmp-gpio-modepin",},
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{ }
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};
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U_BOOT_DRIVER(modepin_gpio) = {
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.name = "modepin_gpio",
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.id = UCLASS_GPIO,
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.ops = &modepin_gpio_ops,
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.of_match = modepin_gpio_ids,
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.probe = modepin_gpio_probe,
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};
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