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bf53344bff
Add DT additions required by U-Boot SPL to bring up the hardware. This includes binman node to generate STM32 Image v2.0 which can be booted by the BootROM, clock entries used by the SPL clock driver during clock tree initialization, and syscon-reboot node so U-Boot can reset the system without having to rely on PSCI call. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
212 lines
2.7 KiB
Plaintext
212 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
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*/
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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pinctrl0 = &pinctrl;
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};
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#if defined(CONFIG_TFABOOT)
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firmware {
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optee {
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bootph-all;
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};
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};
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/* need PSCI for sysreset during board_f */
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psci {
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bootph-some-ram;
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};
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#else
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binman: binman {
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multiple-images;
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spl-stm32 {
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filename = "u-boot-spl.stm32";
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mkimage {
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args = "-T stm32imagev2 -a 0x2ffe0000 -e 0x2ffe0000";
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u-boot-spl {
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no-write-symbols;
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};
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};
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};
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};
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clocks {
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bootph-all;
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clk_hse: ck_hse {
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bootph-all;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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clk_hsi: ck_hsi {
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bootph-all;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: ck_lse {
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bootph-all;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: ck_lsi {
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bootph-all;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_csi: ck_csi {
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bootph-all;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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};
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cpu0_opp_table: cpu0-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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bootph-pre-ram;
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opp-650000000 {
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bootph-pre-ram;
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opp-hz = /bits/ 64 <650000000>;
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opp-microvolt = <1200000>;
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opp-supported-hw = <0x1>;
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};
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opp-1000000000 {
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bootph-pre-ram;
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1350000>;
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opp-supported-hw = <0x2>;
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};
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};
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reboot {
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bootph-all;
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compatible = "syscon-reboot";
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regmap = <&rcc>;
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offset = <0x114>;
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mask = <0x1>;
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};
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#endif
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soc {
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bootph-all;
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ddr: ddr@5a003000 {
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bootph-all;
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compatible = "st,stm32mp13-ddr";
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reg = <0x5A003000 0x550
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0x5A004000 0x234>;
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status = "okay";
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};
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};
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};
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&bsec {
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bootph-all;
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};
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&etzpc {
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bootph-all;
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};
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#if !defined(CONFIG_TFABOOT)
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&cpu0 {
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nvmem-cells = <&part_number_otp>;
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nvmem-cell-names = "part_number";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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#endif
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&gpioa {
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bootph-all;
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};
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&gpiob {
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bootph-all;
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};
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&gpioc {
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bootph-all;
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};
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&gpiod {
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bootph-all;
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};
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&gpioe {
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bootph-all;
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};
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&gpiof {
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bootph-all;
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};
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&gpiog {
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bootph-all;
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};
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&gpioh {
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bootph-all;
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};
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&gpioi {
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bootph-all;
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};
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&iwdg2 {
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bootph-all;
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};
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&pinctrl {
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bootph-all;
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};
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&rcc {
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bootph-all;
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};
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&scmi {
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bootph-all;
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};
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&scmi_clk {
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bootph-all;
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};
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&scmi_reset {
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bootph-all;
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};
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&syscfg {
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bootph-all;
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};
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&usbphyc {
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/* stm32-usbphyc-clk = ck_usbo_48m is a source clock of RCC CCF */
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bootph-all;
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};
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