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Factor out common parts of STM32MP15xx DRAM controller configuration DT description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which describes STM32MP13xx DRAM controller configuration in DT. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
50 lines
758 B
Plaintext
50 lines
758 B
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2018-2025
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*/
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#ifdef CONFIG_SPL
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&ddr {
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clocks = <&rcc AXIDCG>,
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<&rcc DDRC1>,
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<&rcc DDRPHYC>,
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<&rcc DDRCAPB>,
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<&rcc DDRPHYCAPB>;
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clock-names = "axidcg",
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"ddrc1",
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"ddrphyc",
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"ddrcapb",
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"ddrphycapb";
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config-DDR_MEM_COMPATIBLE {
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st,ctl-perf = <
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DDR_SCHED
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DDR_SCHED1
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DDR_PERFHPR1
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DDR_PERFLPR1
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DDR_PERFWR1
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DDR_PCFGR_0
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DDR_PCFGW_0
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DDR_PCFGQOS0_0
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DDR_PCFGQOS1_0
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DDR_PCFGWQOS0_0
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DDR_PCFGWQOS1_0
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>;
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st,phy-reg = <
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DDR_PGCR
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DDR_ACIOCR
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DDR_DXCCR
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DDR_DSGCR
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DDR_DCR
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DDR_ODTCR
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DDR_ZQ0CR1
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DDR_DX0GCR
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DDR_DX1GCR
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>;
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};
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};
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#endif
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#include "stm32mp1-ddr.dtsi"
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