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ed7725c25e
Add dedicated device tree support for eMMC configuration on the Agilex5 SoCDK board, providing an alternative to the default SD card setup. Changes to socfpga_agilex5.dtsi: - - Configure always-on regulator for stable eMMC operation New device tree files: - socfpga_agilex5_socdk_emmc.dts: Main eMMC device tree configuration * Configure for eMMC operation (no-sd, no-sdio, non-removable) * Set 8-bit bus width and high speed capability * Add timing parameters for legacy and SDR modes * Configure voltage supplies for eMMC power and I/O * Add fixed 1.8V regulator for eMMC I/O voltage supply - socfpga_agilex5_socdk_emmc-u-boot.dtsi: U-Boot specific additions * Include common Agilex5 U-Boot configurations * Set SPL boot order with eMMC support * Enable necessary peripherals for boot-time operation Configuration files: - configs/socfpga_agilex5_emmc_defconfig: eMMC-specific configuration * Inherit from base Agilex5 configuration * Disable GPIO regulator support (not needed for fixed eMMC setup) * Set eMMC-specific device tree Build system integration: - Add socfpga_agilex5_socdk_emmc.dtb target to Makefile Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
50 lines
1.3 KiB
Plaintext
50 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*/
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#include "socfpga_agilex5_socdk.dts"
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/ {
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soc {
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emmc_io_1v8_reg: regulator-fixed-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "emmc-io-power";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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};
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};
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&mmc {
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status = "okay";
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no-sd;
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no-sdio;
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disable-wp;
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non-removable;
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cap-mmc-highspeed;
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bus-width = <8>;
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vmmc-supply = <&sd_emmc_power>;
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vqmmc-supply = <&emmc_io_1v8_reg>;
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max-frequency = <200000000>;
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/* eMMC legacy mode timing configuration */
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cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
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cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>;
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cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>;
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cdns,phy-dq-timing-delay-sd-ds = <0x28000001>;
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/* eMMC SDR mode timing configuration */
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cdns,phy-dqs-timing-delay-emmc-sdr = <0x780001>;
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cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x81a40040>;
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cdns,phy-dll-slave-ctrl-emmc-sdr = <0x00000000>;
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cdns,phy-dq-timing-delay-emmc-sdr = <0x10000001>;
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cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0x1800c>;
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cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>;
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cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
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cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>;
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};
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