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9cd3118e4a
On some Qualcomm platforms, such as Dragonwing boards, the WDT_EN register is write-only. Reading it back after enabling the watchdog can return invalid data or cause unexpected behavior. In particular, the check: if (readl(wdt_addr(wdt, WDT_EN)) != 1) may fail even though the watchdog is correctly enabled and running. This leads to misleading error messages and unnecessary failures. Removing the read check ensures compatibility and avoids false negatives on platforms where WDT_EN is not readable. This work builds upon this previous submission: https://lore.kernel.org/u-boot/20250625094607.1348494-1-gopinath.sekar@oss.qualcomm.com/ Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Stefan Roese <sr@denx.de> Link: https://lore.kernel.org/r/20250701065738.1644669-1-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
135 lines
2.7 KiB
C
135 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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* Copyright (c) Linaro Ltd. 2024
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*
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* Authors:
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* Casey Connolly <casey.connolly@linaro.org>
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* Paul Sajna <hello@paulsajna.com>
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*
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* Derived from linux/drivers/watchdog/qcom-wdt.c
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*/
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <wdt.h>
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#include <clk.h>
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#include <asm/io.h>
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enum wdt_reg {
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WDT_RST,
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WDT_EN,
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WDT_STS,
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WDT_BARK_TIME,
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WDT_BITE_TIME,
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};
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struct qcom_wdt_match_data {
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const u32 *offset;
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};
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struct qcom_wdt {
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void __iomem *base;
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ulong clk_rate;
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const u32 *layout;
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};
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static const u32 reg_offset_data_kpss[] = {
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[WDT_RST] = 0x4,
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[WDT_EN] = 0x8,
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[WDT_STS] = 0xC,
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[WDT_BARK_TIME] = 0x10,
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[WDT_BITE_TIME] = 0x14,
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};
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static const struct qcom_wdt_match_data match_data_kpss = {
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.offset = reg_offset_data_kpss,
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};
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static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
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{
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return wdt->base + wdt->layout[reg];
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}
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int qcom_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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struct qcom_wdt *wdt = dev_get_priv(dev);
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ulong bark_timeout_s = ((timeout_ms - 1) * wdt->clk_rate) / 1000;
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ulong bite_timeout_s = (timeout_ms * wdt->clk_rate) / 1000;
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writel(0, wdt_addr(wdt, WDT_EN));
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writel(BIT(0), wdt_addr(wdt, WDT_RST));
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writel(bark_timeout_s, wdt_addr(wdt, WDT_BARK_TIME));
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writel(bite_timeout_s, wdt_addr(wdt, WDT_BITE_TIME));
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writel(BIT(0), wdt_addr(wdt, WDT_EN));
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return 0;
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}
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int qcom_wdt_stop(struct udevice *dev)
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{
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struct qcom_wdt *wdt = dev_get_priv(dev);
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writel(0, wdt_addr(wdt, WDT_EN));
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if (readl(wdt_addr(wdt, WDT_EN))) {
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dev_err(dev, "Failed to disable Qualcomm watchdog!\n");
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return -EIO;
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}
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return 0;
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}
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int qcom_wdt_reset(struct udevice *dev)
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{
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struct qcom_wdt *wdt = dev_get_priv(dev);
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writel(1, wdt_addr(wdt, WDT_RST));
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return 0;
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}
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static int qcom_wdt_probe(struct udevice *dev)
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{
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struct clk clk;
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long rate;
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int ret;
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struct qcom_wdt *wdt = dev_get_priv(dev);
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struct qcom_wdt_match_data *data = (void *)dev_get_driver_data(dev);
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wdt->base = dev_read_addr_ptr(dev);
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wdt->layout = data->offset;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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rate = clk_get_rate(&clk);
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if (rate <= 0)
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return rate < 0 ? (int)rate : -EINVAL;
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wdt->clk_rate = (ulong)rate;
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return 0;
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}
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static const struct wdt_ops qcom_wdt_ops = {
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.start = qcom_wdt_start,
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.stop = qcom_wdt_stop,
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.reset = qcom_wdt_reset,
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};
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static const struct udevice_id qcom_wdt_ids[] = {
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{ .compatible = "qcom,kpss-wdt", .data = (ulong)&match_data_kpss },
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{}
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};
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U_BOOT_DRIVER(qcom_wdt) = {
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.name = "qcom_wdt",
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.id = UCLASS_WDT,
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.of_match = qcom_wdt_ids,
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.ops = &qcom_wdt_ops,
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.probe = qcom_wdt_probe,
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.priv_auto = sizeof(struct qcom_wdt),
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};
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