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53a10c8ce9
Errors reported by GCC 14.2 when enabling FPGA commands and drivers. Also many style fixes as reported by checkpatch.pl on the diffs. Most changes in stratixII.c which has been reorganized as well to avoid the top function prototypes. No functional changes. Signed-off-by: Pieter Van Trappen <pieter.van.trappen@cern.ch> Link: https://lore.kernel.org/r/20250708152455.1214487-4-vtpieter@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
104 lines
2.2 KiB
C
104 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <altera.h>
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#include <log.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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/* Write the RBF data to FPGA via SPI */
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static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
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unsigned long rbf_size)
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{
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struct spi_slave *slave;
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int ret;
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debug("%s (%d): data=%p size=%ld\n",
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__func__, __LINE__, rbf_data, rbf_size);
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/* FIXME: How to get the max. SPI clock and SPI mode? */
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slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
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if (!slave)
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return -1;
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if (spi_claim_bus(slave))
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return -1;
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ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
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SPI_XFER_BEGIN | SPI_XFER_END);
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spi_release_bus(slave);
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return ret;
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}
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/*
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* This is the interface used by FPGA driver.
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* Return 0 for sucess, non-zero for error.
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*/
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int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
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{
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altera_board_specific_func *pfns = desc->iface_fns;
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int cookie = desc->cookie;
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int spi_bus;
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int spi_dev;
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int ret = 0;
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if ((size_t)rbf_data & 0x3) {
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puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
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return -EINVAL;
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}
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/* Run the pre configuration function if there is one */
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if (pfns->pre)
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(pfns->pre)(cookie);
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/* Establish the initial state */
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if (pfns->config) {
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/* De-assert nCONFIG */
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(pfns->config)(false, true, cookie);
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/* nConfig minimum low pulse width is 2us */
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udelay(200);
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/* Assert nCONFIG */
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(pfns->config)(true, true, cookie);
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/* nCONFIG high to first rising clock on DCLK min 1506 us */
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udelay(1600);
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}
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/* Write the RBF data to FPGA */
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if (pfns->write) {
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/*
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* Use board specific data function to write bitstream
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* into the FPGA
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*/
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ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
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} else {
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/*
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* Use common SPI functions to write bitstream into the
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* FPGA
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*/
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spi_bus = COOKIE2SPI_BUS(cookie);
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spi_dev = COOKIE2SPI_DEV(cookie);
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ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
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}
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if (ret)
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return ret;
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/* Check done pin */
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if (pfns->done) {
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ret = (pfns->done)(cookie);
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if (ret)
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printf("Error: DONE not set (ret=%d)!\n", ret);
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}
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return ret;
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}
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