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d680ac6cfd
Add iMX95 blkctrl clock driver which implements clocks for HSIOMIX blkctrl and LVDS blkctrl. Since multiple blkctrl device for different blkctrl may be enabled, and each has dedicated clock id from 0. We must enable CLK_AUTO_ID to avoid conflict on clock id. Signed-off-by: Ye Li <ye.li@nxp.com>
29 lines
1.0 KiB
Makefile
29 lines
1.0 KiB
Makefile
# Copyright 2018 NXP
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#
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o
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obj-$(CONFIG_$(PHASE_)CLK_IMX6Q) += clk-imx6q.o
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obj-$(CONFIG_$(PHASE_)CLK_IMX6UL) += clk-imx6ul.o
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obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
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ifdef CONFIG_CLK_IMX8
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obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
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obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
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endif
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obj-$(CONFIG_$(PHASE_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
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clk-composite-8m.o
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obj-$(CONFIG_$(PHASE_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
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clk-composite-8m.o
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obj-$(CONFIG_$(PHASE_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
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clk-composite-8m.o
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obj-$(CONFIG_$(PHASE_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
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clk-composite-8m.o
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obj-$(CONFIG_$(PHASE_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \
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clk-gate-93.o clk-composite-93.o
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obj-$(CONFIG_$(PHASE_)CLK_IMXRT1020) += clk-imxrt1020.o
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obj-$(CONFIG_$(PHASE_)CLK_IMXRT1050) += clk-imxrt1050.o
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obj-$(CONFIG_$(PHASE_)CLK_IMXRT1170) += clk-imxrt1170.o
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obj-$(CONFIG_CLK_IMX95_BLKCTRL) += clk-imx95-blkctrl.o
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