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9bde0c1da5
Trivially fix the following warnings in sandbox DTs, which show up with DTC 1.7.2. Fill in the missing address and adjust emulated I2C address to fit the 7bit address limit: " arch/sandbox/dts/sandbox.dtsi:138.30-140.5: Warning (i2c_bus_reg): /i2c@0/sandbox_pmic: I2C bus unit address format error, expected "40" arch/sandbox/dts/sandbox.dtsi:146.18-161.5: Warning (i2c_bus_reg): /i2c@0/emul: I2C bus unit address format error, expected "ff" arch/sandbox/dts/sandbox.dtsi:148.4-17: Warning (i2c_bus_reg): /i2c@0/emul:reg: I2C address must be less than 7-bits, got "0xff". Set I2C_TEN_BIT_ADDRESS for 10 bit addresses or fix the property " " arch/sandbox/dts/.test.dtb.pre.tmp:912.18-926.5: Warning (i2c_bus_reg): /i2c@0/emul: I2C bus unit address format error, expected "ff" arch/sandbox/dts/.test.dtb.pre.tmp:913.4-17: Warning (i2c_bus_reg): /i2c@0/emul:reg: I2C address must be less than 7-bits, got "0xff". Set I2C_TEN_BIT_ADDRESS for 10 bit addresses or fix the property arch/sandbox/dts/.test.dtb.pre.tmp:928.30-931.5: Warning (i2c_bus_reg): /i2c@0/sandbox_pmic: I2C bus unit address format error, expected "40" " Fix up pmic test to match. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Heiko Schocher <hs@nabladev.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
128 lines
3.0 KiB
C
128 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Tests for the driver model pmic API
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*
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* Copyright (c) 2015 Samsung Electronics
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* Przemyslaw Marczak <p.marczak@samsung.com>
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*/
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#include <errno.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <fsl_pmic.h>
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#include <malloc.h>
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#include <dm/device-internal.h>
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#include <dm/root.h>
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#include <dm/test.h>
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#include <dm/uclass-internal.h>
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#include <dm/util.h>
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#include <power/pmic.h>
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#include <power/sandbox_pmic.h>
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#include <test/test.h>
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#include <test/ut.h>
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/* Test PMIC get method */
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static inline int power_pmic_get(struct unit_test_state *uts, char *name)
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{
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struct udevice *dev;
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ut_assertok(pmic_get(name, &dev));
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ut_assertnonnull(dev);
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/* Check PMIC's name */
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ut_asserteq_str(name, dev->name);
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return 0;
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}
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/* Test PMIC get method */
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static int dm_test_power_pmic_get(struct unit_test_state *uts)
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{
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power_pmic_get(uts, "sandbox_pmic@40");
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return 0;
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}
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DM_TEST(dm_test_power_pmic_get, UTF_SCAN_FDT);
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/* PMIC get method - MC34708 - for 3 bytes transmission */
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static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
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{
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power_pmic_get(uts, "pmic@41");
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return 0;
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}
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DM_TEST(dm_test_power_pmic_mc34708_get, UTF_SCAN_FDT);
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/* Test PMIC I/O */
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static int dm_test_power_pmic_io(struct unit_test_state *uts)
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{
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const char *name = "sandbox_pmic@40";
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uint8_t out_buffer, in_buffer;
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struct udevice *dev;
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int reg_count, i;
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ut_assertok(pmic_get(name, &dev));
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reg_count = pmic_reg_count(dev);
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ut_asserteq(reg_count, SANDBOX_PMIC_REG_COUNT);
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/*
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* Test PMIC I/O - write and read a loop counter.
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* usually we can't write to all PMIC's registers in the real hardware,
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* but we can to the sandbox pmic.
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*/
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for (i = 0; i < reg_count; i++) {
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out_buffer = i;
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ut_assertok(pmic_write(dev, i, &out_buffer, 1));
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ut_assertok(pmic_read(dev, i, &in_buffer, 1));
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ut_asserteq(out_buffer, in_buffer);
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}
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return 0;
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}
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DM_TEST(dm_test_power_pmic_io, UTF_SCAN_FDT);
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#define MC34708_PMIC_REG_COUNT 64
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#define MC34708_PMIC_TEST_VAL 0x125534
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static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
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{
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struct udevice *dev;
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int reg_count;
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ut_assertok(pmic_get("pmic@41", &dev));
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/* Check number of PMIC registers */
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reg_count = pmic_reg_count(dev);
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ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
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return 0;
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}
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DM_TEST(dm_test_power_pmic_mc34708_regs_check, UTF_SCAN_FDT);
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static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
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{
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struct udevice *dev;
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int val;
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ut_assertok(pmic_get("pmic@41", &dev));
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/* Check if single 3 byte read is successful */
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val = pmic_reg_read(dev, REG_POWER_CTL2);
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ut_asserteq(val, 0x422100);
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/* Check if RW works */
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val = 0;
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ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
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ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
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val = pmic_reg_read(dev, REG_RTC_TIME);
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ut_asserteq(val, MC34708_PMIC_TEST_VAL);
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pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
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val = pmic_reg_read(dev, REG_POWER_CTL2);
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ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
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return 0;
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}
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DM_TEST(dm_test_power_pmic_mc34708_rw_val, UTF_SCAN_FDT);
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