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60a99d5ca3
Let's introduce the Generic System Interconnect subsystem based on the counterpart Linux framework which is used to vote for bandwidth across multiple SoC busses. Documentation for the Linux Generic System Interconnect Subsystem can be found at [1]. Each bus endpoints are materialised as "nodes" which are linked together, and the DT will specify a pair of nodes to enable and set a bandwidth on the route between those endpoints. The hardware resources that provide those nodes and provides the way to vote for the bandwidth are called "providers". The Interconnect uclass code is heavily based on the Linux one, with some small differences: - nodes are allocated as udevices instead of Linux idr_alloc() - tag management is minimal, only normal xlate is supported - getting nodes states at probe is not implemented - providers are probed on demand while the nodes links are traversed - nodes are populated on bind - id management is simplified, static IDs and dynamics IDs can be used - identical consume API as Linux, only implementation differs Fully tested with associated DM test suite. [1] https://docs.kernel.org/driver-api/interconnect.html Link: https://patch.msgid.link/20251120-topic-interconnect-next-v5-1-e8a82720da5d@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
171 lines
6.7 KiB
C
171 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2013 Google, Inc
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*
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* (C) Copyright 2012
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* Pavel Herrmann <morpheus.ibis@gmail.com>
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*
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* Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* Authors:
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* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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*/
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#ifndef _DM_UCLASS_ID_H
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#define _DM_UCLASS_ID_H
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/* TODO(sjg@chromium.org): this could be compile-time generated */
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enum uclass_id {
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/* These are used internally by driver model */
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UCLASS_ROOT = 0,
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UCLASS_DEMO,
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UCLASS_TEST,
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UCLASS_TEST_FDT,
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UCLASS_TEST_FDT_MANUAL,
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UCLASS_TEST_BUS,
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UCLASS_TEST_PROBE,
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UCLASS_TEST_DUMMY,
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UCLASS_TEST_DEVRES,
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UCLASS_TEST_ACPI,
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UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
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UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
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UCLASS_I2C_EMUL_PARENT, /* parent for I2C device emulators */
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UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
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UCLASS_PCI_EMUL_PARENT, /* parent for PCI device emulators */
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UCLASS_USB_EMUL, /* sandbox USB bus device emulator */
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UCLASS_AXI_EMUL, /* sandbox AXI bus device emulator */
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/* U-Boot uclasses start here - in alphabetical order */
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UCLASS_ACPI_PMC, /* (x86) Power-management controller (PMC) */
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UCLASS_ADC, /* Analog-to-digital converter */
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UCLASS_AES, /* AES cryptographic engine */
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UCLASS_AHCI, /* SATA disk controller */
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UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */
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UCLASS_AXI, /* AXI bus */
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UCLASS_BLK, /* Block device */
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UCLASS_BLKMAP, /* Composable virtual block device */
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UCLASS_BOOTCOUNT, /* Bootcount backing store */
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UCLASS_BOOTDEV, /* Boot device for locating an OS to boot */
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UCLASS_BOOTMETH, /* Bootmethod for booting an OS */
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UCLASS_BOOTSTD, /* Standard boot driver */
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UCLASS_BUTTON, /* Button */
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UCLASS_CACHE, /* Cache controller */
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UCLASS_CLK, /* Clock source, e.g. used by peripherals */
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UCLASS_CPU, /* CPU, typically part of an SoC */
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UCLASS_CROS_EC, /* Chrome OS EC */
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UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
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UCLASS_DMA, /* Direct Memory Access */
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UCLASS_DSA, /* Distributed (Ethernet) Switch Architecture */
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UCLASS_DSI_HOST, /* Display Serial Interface host */
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UCLASS_ECDSA, /* Elliptic curve cryptographic device */
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UCLASS_EFI_LOADER, /* Devices created by UEFI applications */
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UCLASS_EFI_MEDIA, /* Devices provided by UEFI firmware */
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UCLASS_ETH, /* Ethernet device */
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UCLASS_ETH_PHY, /* Ethernet PHY device */
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UCLASS_EXTCON, /* External Connector Class */
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UCLASS_EXTENSION, /* Extension board */
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UCLASS_FFA, /* Arm Firmware Framework for Armv8-A */
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UCLASS_FFA_EMUL, /* sandbox FF-A device emulator */
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UCLASS_FIRMWARE, /* Firmware */
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UCLASS_FPGA, /* FPGA device */
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UCLASS_FUZZING_ENGINE, /* Fuzzing engine */
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UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
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UCLASS_FWU_MDATA, /* FWU Metadata Access */
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UCLASS_GPIO, /* Bank of general-purpose I/O pins */
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UCLASS_HASH, /* Hash device */
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UCLASS_HWSPINLOCK, /* Hardware semaphores */
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UCLASS_HOST, /* Sandbox host device */
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UCLASS_I2C, /* I2C bus */
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UCLASS_I2C_EEPROM, /* I2C EEPROM device */
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UCLASS_I2C_GENERIC, /* Generic I2C device */
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UCLASS_I2C_MUX, /* I2C multiplexer */
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UCLASS_I2S, /* I2S bus */
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UCLASS_I3C, /* I3C bus */
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UCLASS_IDE, /* IDE device */
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UCLASS_IOMMU, /* IOMMU */
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UCLASS_INTERCONNECT, /* Interconnect */
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UCLASS_ICC_NODE, /* Interconnect Node */
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UCLASS_IRQ, /* Interrupt controller */
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UCLASS_KEYBOARD, /* Keyboard input device */
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UCLASS_LED, /* Light-emitting diode (LED) */
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UCLASS_LPC, /* x86 'low pin count' interface */
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UCLASS_MAILBOX, /* Mailbox controller */
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UCLASS_MASS_STORAGE, /* Mass storage device */
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UCLASS_MDIO, /* MDIO bus */
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UCLASS_MDIO_MUX, /* MDIO MUX/switch */
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UCLASS_MEMORY, /* Memory Controller device */
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UCLASS_SM, /* Secure Monitor driver */
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UCLASS_MISC, /* Miscellaneous device */
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UCLASS_MMC, /* SD / MMC card or chip */
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UCLASS_MOD_EXP, /* RSA Mod Exp device */
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UCLASS_MTD, /* Memory Technology Device (MTD) device */
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UCLASS_MUX, /* Multiplexer device */
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UCLASS_NOP, /* No-op devices */
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UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
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UCLASS_NVME, /* NVM Express device */
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UCLASS_NVMXIP, /* NVM XIP devices */
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UCLASS_P2SB, /* (x86) Primary-to-Sideband Bus */
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UCLASS_PANEL, /* Display panel, such as an LCD */
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UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
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UCLASS_PARTITION, /* Logical disk partition device */
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UCLASS_PCH, /* x86 platform controller hub */
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UCLASS_PCI, /* PCI bus */
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UCLASS_PCI_EP, /* PCI endpoint device */
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UCLASS_PCI_GENERIC, /* Generic PCI bus device */
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UCLASS_PHY, /* Physical Layer (PHY) device */
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UCLASS_PINCONFIG, /* Pin configuration node device */
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UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
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UCLASS_PMIC, /* PMIC I/O device */
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UCLASS_POWER_DOMAIN, /* (SoC) Power domains */
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UCLASS_PVBLOCK, /* Xen virtual block device */
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UCLASS_PWM, /* Pulse-width modulator */
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UCLASS_PWRSEQ, /* Power sequence device */
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UCLASS_QFW, /* QEMU firmware config device */
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UCLASS_RAM, /* RAM controller */
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UCLASS_REBOOT_MODE, /* Reboot mode */
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UCLASS_REGULATOR, /* Regulator device */
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UCLASS_REMOTEPROC, /* Remote Processor device */
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UCLASS_RESET, /* Reset controller device */
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UCLASS_RKMTD, /* Rockchip MTD device */
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UCLASS_RNG, /* Random Number Generator */
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UCLASS_RTC, /* Real time clock device */
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UCLASS_SCMI_AGENT, /* Interface with an SCMI server */
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UCLASS_SCMI_BASE, /* Interface for SCMI Base protocol */
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UCLASS_SCSI, /* SCSI device */
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UCLASS_SERIAL, /* Serial UART */
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UCLASS_SIMPLE_BUS, /* Bus with child devices */
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UCLASS_SMEM, /* Shared memory interface */
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UCLASS_SOC, /* SOC Device */
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UCLASS_SOUND, /* Playing simple sounds */
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UCLASS_SPI, /* SPI bus */
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UCLASS_SPI_FLASH, /* SPI flash */
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UCLASS_SPI_GENERIC, /* Generic SPI flash target */
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UCLASS_SPMI, /* System Power Management Interface bus */
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UCLASS_SYSCON, /* System configuration device */
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UCLASS_SYSINFO, /* Device information from hardware */
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UCLASS_SYSRESET, /* System reset device */
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UCLASS_TCPM, /* TypeC port manager */
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UCLASS_TEE, /* Trusted Execution Environment device */
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UCLASS_THERMAL, /* Thermal sensor */
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UCLASS_TIMER, /* Timer device */
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UCLASS_TPM, /* Trusted Platform Module TIS interface */
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UCLASS_UFS, /* Universal Flash Storage */
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UCLASS_USB, /* USB bus */
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UCLASS_USB_DEV_GENERIC, /* USB generic device */
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UCLASS_USB_HUB, /* USB hub */
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UCLASS_USB_GADGET_GENERIC, /* USB generic device */
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UCLASS_VIDEO, /* Video or LCD device */
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UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */
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UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */
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UCLASS_VIDEO_OSD, /* On-screen display */
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UCLASS_VIRTIO, /* VirtIO transport device */
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UCLASS_W1, /* Dallas 1-Wire bus */
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UCLASS_W1_EEPROM, /* one-wire EEPROMs */
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UCLASS_WDT, /* Watchdog Timer driver */
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UCLASS_COUNT,
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UCLASS_INVALID = -1,
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};
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#endif
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