Balaji Selvanathan f4886799a0 clk: qcom: sa8775p: Fix USB clock configuration and add resets
Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")

Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260113065856.3287772-1-balaji.selvanathan@oss.qualcomm.com
[casey: indentation fix]
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-01-14 16:25:09 +01:00
..
2025-10-29 12:27:33 +01:00
2025-10-29 12:27:33 +01:00