This patch adds pwm support for MediaTek MT7987 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Some drivers set DM_FLAG_PROBE_AFTER_BIND, this does nothing since it's
only every applied on a per-device basis.
Remove the flags.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Pass DBSC5 udevice and MODEMR0 register values to board specific
function dbsc5_get_board_data(). The board specific implementation
of dbsc5_get_board_data() can return struct renesas_dbsc5_board_config
which matches the board based on the content of MODEMR0 or content
of DT accessible via the udevice.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Extract wait for completion code from dbsc5_send_dbcmd2() into
new separate function dbsc5_wait_dbwait(). This extracted code
can be used to implement MR register read in the future.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Update dbsc5_send_dbcmd2() such that it takes multiple parameters
instead of one magic register content value. These parameters are
used to form the same resulting register value internally in the
dbsc5_send_dbcmd2() function, but from well defined input constants.
The new input constants are the operation code, channel, rank, and
operation argument. The argument is operation code specific, therefore
it is still a 16-bit magic number, but the rest of the arguments are
now split up. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Rename dbsc5_ddr_register_read() to dbsc5_ddr_register_mr27_mr57_read()
and dbsc5_ddr_register_set() to dbsc5_ddr_register_mr28_set() to make
it clear what those functions really do. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Assorted fixes, refactorings and additions that are ready, and shave
off some load from upcoming series'.
Improves MMC performance on D1/T113 (missed clock divider), enables
eMMC access on the H616 family (never worked, many thanks to Jernej for
the fix!), DRAM detection fixes for the H616 (now reportedly stable).
Some patches for the upcoming Allwinner A133 SoC support: a few
refactorings, plus the DM clock and pinctrl driver. The DRAM init
routines work, but need some more polishing, that also holds back the
actual enablement patch, which will hopefully follow for v2025.07 still.
Also some preparatory patches for the Allwinner A523 SoC support, for
now just to improve the FEL save/restore code. There will be more patches
coming up for this, ideally also in the coming cycle still.
Gitlab CI passed, and I booted that briefly on some boards.
Cards should always be reset and threshold set. This fixes eMMC on H616.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
[Andre: use macro-defined offsets to fix build on older SoCs]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.
Add the required mapping between the pinmux group strings and their
respective mux value, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can build on the
names already used there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.
Add support for the CCU, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can already use the
existing binding headers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Some of the X-Power AXP PMICs can be ordered with an alternative I2C
address, for instance an AXP717 could be shipped with address 0x34 or
with address 0x35. Similarly the AXP803 lists two possible addresses.
For DM (DT) based drivers this is no problem, but the Allwinner SPL
code relies on exactly one hardcoded address per PMIC so far.
Add a Kconfig variable that holds the I2C address used by the PMIC
accessed in the SPL, and provide the (mostly only one) supported address
as its default, for the PMICs we use. Boards using the other address
can easily set this in their defconfig.
This effectively moves the hardcoding from C code to Kconfig.
That enables to use the AXP717 on some boards with the new Allwinner
A523 chip, which use the other I2C address there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The AXP803 has been around for about a decade now, but so far we didn't
need SPL support, since the DRAM rail was wired up correctly at reset.
Now some boards using the A133 SoC use the (compatible) AXP707 with DDR4
memory, which requires the SPL to set the required 1.1V voltage manually.
Add the descriptions for the DC/DC regulators of the AXP803, and enable
that when CONFIG_AXP803_POWER is enabled.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
On the Allwinner D1/R528/T113-s3 SoCs the MMC clock source selected by
mux value 1 is PLL_PERIPH0(1x), not (2x), as in the other SoCs.
But we have still the hidden divisor of 2 in the MMC mod clock, so
need to explicitly compensate for that on those SoCs.
This leads to the actually programmed clock rate to be double compared
to before, which increases the MMC performance on those SoCs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The EFI HTTP boot puts the ISO installer image at some location in
memory. Information about this image has to be passed on to the OS
kernel, which is done by adding a persistent memory(pmem) node to the
devicetree(DT) that is passed to the OS. The OS kernel then gets
information about the presence of this ISO image and proceeds with the
installation.
In U-Boot, this ISO image gets mounted as a memory mapped blkmap
device slice, with the 'preserve' attribute. Add a helper function
which iterates through all such slices, and invokes a callback. The
callback adds the pmem node to the DT and removes the corresponding
memory region from the EFI memory map. Invoke this helper function as
part of the DT fixup which happens before booting the OS.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Tobias Waldekranz <tobias@waldekranz.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Some blkmap memory mapped devices might have to be relevant even
after U-Boot passes control to the next image as part of the platform
boot. An example of such a mapping would be an OS installer ISO image,
information for which has to be provided to the OS kernel. Use the
'preserve' attribute for such mappings. The code for adding a pmem
node to the device-tree then checks if this attribute is set, and adds
a node only for mappings which have this attribute.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Tobias Waldekranz <tobias@waldekranz.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Add information about the type of blkmap slices as an attribute in the
corresponding slice structure. Put information in the blkmap slice
structure to identify if it is associated with a memory or linear
mapped device. Which can then be used to take specific action based on
the type of the blkmap slice.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Tobias Waldekranz <tobias@waldekranz.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Much of the data that is display by imx8_cpu.c is also displayed from
arch/arm/mach-imx/cpu.c, except the temperature grade and active
temperature are only displayed when SoC is an i.MX9. Since IMX9 now
implies IMX_TMU, change this to check for IMX_TMU in the same way
it's done in mach-imx/cpu.c to enable displaying this information
for any SoC with either of this config enabled.
Since additional text may appear due to this commit, remove
the extra space in the message displaying the temperature
grade.
Before:
CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz
Model: Beacon EmbeddedWorks i.MX8MPlus Development kit
After:
CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz
CPU: Industrial temperature grade (-40C to 105C) at 28C
Model: Beacon EmbeddedWorks i.MX8MPlus Development kit
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The imx8_cpu is capable of running on IMX8, IMX8M, and IMX9
families, but the CPU list is limited on the 8M variants. Expand
this list to show more variants and their respective names.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
take 2
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEtlGhRjxqvtBpDFXNBYMxKxlfZLYFAmfhkqIACgkQBYMxKxlf
ZLY5Ig/+J9R0ZC9qJxQXZHANfWRUsCwn9UDnc/cYgo6eD/E87Tgdr85vlH44JOh9
wka2ysn6H4IaN7Ca4435GUjntvuhJ85HLXhbBuQXOT27fHSIV0MJq94jvGwDzSps
IOy9JSYHhbs5tP33ekXfLYlL60BFqcTm22VXUfAXD9mMkDonbh4vq1LPxskVj8iq
85k5F2GyFm5cU4H5nQpgI+6+LQSJ/FlraOGNOYQj7MiQzTxPkWL6hC+p+9RuJAbt
NLJiDd3oQUgpo9/jQseteNXrUfQYsUmuzjrz71V2Z9saIHKw+AuVcnr/EanynjiJ
JjKdQ3Xmu3zwdTGP3/c/ZIxy1vKq4qoVnjzHo8x/am7euPNnj9lS7liq618/qhtv
AuCf6SSpXqKFMejXn/mF28sO0merI5oM3OB7AEL+BOH5HIaNr39PyAQ+8HKh5tmb
7lB1z/LjSPvpapQOZqj2XTBcNuxFT6rD4Nl5CFlJLjcGdMd6BRpCulE8z/53VSwH
FDEi0pqsN4No1anA8XMial7BEtCrM1e9NO3X+RRXCbxGZHa37fwlFmzTbpqUZcRA
iv0YmXvv2PT3+W/tuwS8d2ZgTSctFSAoKd5B9iuDiuNko/teUbKFREY7E/rB7Oky
AcNUT6ILmsqNg+BnkXu3Z+NP+Ms30FOxK/pEptek0vfLwJuAhg8=
=2n9a
-----END PGP SIGNATURE-----
Merge tag 'qcom-next-20250324' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next
qcom-next-20230324:
* msm8916 gets proper sysreset and spin-table support
* The first new IPQ platform is added - the IPQ9574. The IPQ series are
used in routers. The flashing process is also documented
* mach-snapdragon gains the ability to boot with an internal FDT and
still parse memory from an externally provided one
* SC7280 gets a pinctrl driver and various clock driver improvements.
* Qualcom clock drivers will now actually return an error when
attempting
to enable a clock which isn't described.
* Qualcomm pinctrl drivers will now return an error when attempting to
configure an invalid function mux
Pass struct udevice * into imx_clk_fixed_factor*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <marex@denx.de>
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut <marex@denx.de>
Use U-Boot specific struct udevice instead of Linux compatibility
struct device in clk-fixed-factor registration.
Signed-off-by: Marek Vasut <marex@denx.de>
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut <marex@denx.de>
Pass struct udevice * into imx_clk_divider*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <marex@denx.de>
Use U-Boot specific struct udevice instead of Linux compatibility
struct device in clk-divider clock registration.
Signed-off-by: Marek Vasut <marex@denx.de>
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut <marex@denx.de>
Pass struct udevice * into imx_clk_pllv3*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <marex@denx.de>
Convert clock-osc-24m back to osc_24m and clock-osc-32k back to osc_32k.
These are the clock which match clock tables in Linux. This is now
possible because the clock drivers now resolve clock names based on
clock-names DT property in the CCM DT node.
Signed-off-by: Marek Vasut <marex@denx.de>
Pass struct udevice * into imx_clk_composite*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <marex@denx.de>
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut <marex@denx.de>
Use U-Boot specific struct udevice instead of Linux compatibility
struct device in clk-composite registration.
Signed-off-by: Marek Vasut <marex@denx.de>
Pass U-Boot specific struct udevice pointer to clock parent device
to clk_register_gate*(), so clk_register_gate*() can access the parent
udevice.
Signed-off-by: Marek Vasut <marex@denx.de>
Pass struct udevice * into imx_clk_gate*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <marex@denx.de>
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut <marex@denx.de>
Use U-Boot specific struct udevice instead of Linux compatibility
struct device in gate2 clock registration.
Signed-off-by: Marek Vasut <marex@denx.de>
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut <marex@denx.de>
Pass U-Boot specific struct udevice pointer to clock parent device
to clk_register_mux(), so clk_register_mux() can access the parent
udevice.
Signed-off-by: Marek Vasut <marex@denx.de>
Pass struct udevice * into imx_clk_mux*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut <marex@denx.de>
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut <marex@denx.de>
Neither clk_register_mux_table() nor clk_hw_register_mux_table()
are called outside of clk-mux.c , fold both into clk_register_mux().
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
