3 Commits

Author	SHA1	Message	Date
Ley Foon Tan	456d45261b	ddr: altera: Stratix10: Add ECC memory scrubbing ... Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>	2019-04-17 22:20:17 +02:00
Dalon Westergreen	02d8d32591	socfpga: stratix10: fix sdram_calculate_size ... Incorrect type of size variable results in 0 being returned for sdram sizes greater than or equal to 4GB. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>	2018-09-15 03:17:01 +02:00
Ley Foon Tan	0bc28b7cb8	ddr: altera: stratix10: Add DDR support for Stratix10 SoC ... Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>	2018-07-12 09:22:12 +02:00