93586 Commits

Author SHA1 Message Date
Heiko Stuebner
a764eb156a arm64: dts: rockchip: enable gpu on rk3588-tiger
Enable the mali gpu node and add the som-specific supply-regulator.

Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Link: https://lore.kernel.org/r/20240327112120.1181570-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: f5256f8ed4b729c3ab9d9cd7d406313773484b59 ]

(cherry picked from commit 27350b241eafea37dc94743cd9c5dd83295faca9)
2024-06-14 17:13:35 +08:00
Quentin Schulz
724d3c686c rockchip: ringneck-px30: fix TPL_MAX_SIZE
Ringneck was mistakenly set to allow up to 128KiB for the TPL code size
while PX30 SoC only has 16KiB of SRAM.

Therefore, let's use the default value of TPL_MAX_SIZE from the SoC
(which is 10KiB) so that the max code size is actually checked and
useful.

Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:11:29 +08:00
Quentin Schulz
2ce40542e0 power: rk8xx: properly print all supported PMICs name
The ID of the PMIC is stored in the 2 16b registers but the only part
that matters right now is the 3 MSB, which make the 3 digits (in hex) of
the part number.

Right now, only RK808 was properly displayed, with this all currently
supported PMICs should display the proper part number.

Additionally, when the PMIC variant is not found, print that value
instead of the masked unshifted value as all PMICs we support for now
have their LSB ignored to represent the actual part number.

Tested on RK806 (RK3588 Jaguar), RK808 (RK3399 Puma) and RK809 (PX30
Ringneck).

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:11:29 +08:00
Quentin Schulz
aefdec5277 rockchip: px30-ringneck: Update SPL_PAD_TO Kconfig option
On px30-ringneck the FIT payload is located at sector 0x200 compared to
the more Rockchip common sector 0x4000 offset:
	SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200

Because FIT payload is located at sector 0x200 and the TPL+SPL is
located at sector 64, the combined size of TPL+SPL cannot take up more
than 224KiB:
	(0x200 - 64) x 512 = 0x38000 (224 KiB)

Adjust SPL_PAD_TO to match the used 0x200 sector offset.

While at it, update the px30-ringneck-u-boot.dtsi to remove the now
unnecessary override of simple-bin:fit:offset since SPL_PAD_TO matches
with the current formula.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:11:29 +08:00
Quentin Schulz
b58e0d304b rockchip: rk3399-puma: remove unnecessary simple-bin:fit:offset override
Since commit 6007b69d544e ("rockchip: rk3399-puma: Update SPL_PAD_TO
Kconfig option"), SPL_PAD_TO matches
(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512 and the default
value for simple-bin:fit:offset in rockchip-u-boot.dtsi is
SPL_PAD_TO, so let's remove this override.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:11:29 +08:00
Quentin Schulz
eeaa46a70e rockchip: rk3399-puma: remove default value from defconfig
CONFIG_ENV_OFFSET already defaults to 0x3F8000, however it is stored in
lowercase hexdigits instead of uppercase like in the defconfig.

No change in behavior intended.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:11:29 +08:00
Quentin Schulz
67f87e215c rockchip: jaguar-rk3588: use default env size for Rockchip on MMC
The default env size is 0x8000 when building for Rockchip SoCs with
support for environment stored in MMC.

Jaguar hasn't entered mass production just yet, so it's a breaking
change we can afford in the name of consistency.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:11:29 +08:00
Jianfeng Liu
40b573e4f6 board: rockchip: add ArmSoM Sige7 Rk3588 board
ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by
ArmSoM.

There are two variants depending on the DRAM size : 8G and 16G.

Specification:

    Rockchip Rk3588 SoC
    4x ARM Cortex-A76, 4x ARM Cortex-A55
    8/16GB memory LPDDR4x
    Mali G610MC4 GPU
    2x MIPI CSI 2 multiple lanes connector
    64GB/128GB on board eMMC
    uSD slot
    1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C
    1x HDMI 2.1 output
    2x 2.5 Gbps Ethernet port
    40-pin IO header including UART, SPI and I2C
    USB PD over USB Type-C
    Size: 92mm x 62mm

Kernel commit:
81c828a67c78 (arm64: dts: rockchip: Add ArmSom Sige7 board)

Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Jianfeng Liu
7a53abb183 rockchip: rk3588: Remove USB3 DRD nodes in u-boot.dtsi
After we sync USB3 DRD nodes from v6.10-rc1, these obsolete nodes
can be removed.

Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Jianfeng Liu
809b5167df arm64: dts: rockchip: Add ArmSom Sige7 board
Specification:
        Rockchip Rk3588 SoC
        4x ARM Cortex-A76, 4x ARM Cortex-A55
        8/16/32GB Memory LPDDR4/LPDDR4x
        Mali G610MP4 GPU
        2× MIPI-CSI Connector
        1× MIPI-DSI Connector
        1x M.2 Key M (PCIe 3.0 4-lanes)
        2x RTL8125 2.5G Ethernet
        Onboard AP6275P for WIFI6/BT5
        32GB/64GB/128GB eMMC
        MicroSD card slot
        1x USB2.0, 1x USB3.0 Type-A, 1x US3.0 Type-C
        1x HDMI Output, 1x type-C DP Output

Functions work normally:
        USB2.0 Host
        USB3.0 Type-A Host
        M.2 Key M (PCIe 3.0 4-lanes)
        2x RTL8125 2.5G Ethernet
        eMMC
        MicroSD card

More information can be obtained from the following website
        https://docs.armsom.org/armsom-sige7

Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Weizhao Ouyang <weizhao.ouyang@arm.com>
Link: https://lore.kernel.org/r/20240420034300.176920-4-liujianfeng1994@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 81c828a67c78bb03ea75819c417c93c7f3d637b5 ]

(cherry picked from commit d427a11542bcf5364a5260280e077f0a2e030dcb)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Niklas Cassel
95967c4a74 arm64: dts: rockchip: add rk3588 pcie and php IOMMUs
The mmu600_pcie is connected with the five PCIe controllers.
The mmu600_php is connected with the USB3 controller, the GMAC
controllers, and the SATA controllers.

See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual).

The IOMMUs are disabled by default, as further patches are needed to
program the SID/SSIDs in to the IOMMUs.

iommu: Default domain type: Translated
iommu: DMA domain TLB invalidation policy: strict mode
arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf)
arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq
arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq
arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs

Additionally, the IOMMU correctly triggers an IOMMU fault when
a PCIe device performs a write (since the device hasn't been
assigned a SID/SSID):
arm-smmu-v3 fc900000.iommu: event 0x02 received:
arm-smmu-v3 fc900000.iommu:      0x0000010000000002
arm-smmu-v3 fc900000.iommu:      0x0000000000000000
arm-smmu-v3 fc900000.iommu:      0x0000000000000000
arm-smmu-v3 fc900000.iommu:      0x0000000000000000

While this doesn't provide much value as is, having the devices as
disabled in the device tree will allow developers to see that the rk3588
actually has IOMMUs on the SoC.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 ]

(cherry picked from commit ea9a34aa0d786cbf4b87f1ba528e69b07219738f)
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Sebastian Reichel
99ebe21169 arm64: dts: rockchip: add USB3 DRD controllers on rk3588
Add both USB3 dual-role controllers to the RK3588 devicetree.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 33f393a2a990e16f56931ca708295f31d2b44415 ]

(cherry picked from commit c7ed588e14f7dd04a92fb55f12680f94c7b14edf)
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Sebastian Reichel
db60a2fc44 arm64: dts: rockchip: add USBDP phys on rk3588
Add both USB3-DisplayPort PHYs to RK3588 SoC DT.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: e18e5e8188f2671abf63abe7db5f21555705130f ]

(cherry picked from commit 5110caca9865718616cf7093ed4a9a1bc54780db)
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Sebastian Reichel
e1a374d584 arm64: dts: rockchip: reorder usb2phy properties for rk3588
Reorder common DT properties alphabetically for usb2phy, according
to latest DT style rules.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: abe68e0ca71dddce0e5419e35507cb464d61870d ]

(cherry picked from commit f6835a60a8a28ff14ffb3dd80c99ce1c137d06c5)
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Sebastian Reichel
b88ddd5a82 arm64: dts: rockchip: fix usb2phy nodename for rk3588
usb2-phy should be named usb2phy according to the DT binding,
so let's fix it up accordingly.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 4e07a95f7402de092cd71b2cb96c69f85c98f251 ]

(cherry picked from commit 5a3e4638492497ae81b9bd4a8627f4727e312ccc)
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Diederik de Haas
376b0d0515 arm64: dts: rockchip: Fix ordering of nodes on rk3588s
Fix the ordering of the main nodes by sorting them alphabetically and
then the ones with a memory address sequentially by that address.

Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: cbb97fe18e299ece1c0074924c630de6a19b320f ]

(cherry picked from commit bbf7c16f2f1208b96349f6f6648b69cfaa1a482b)
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Boris Brezillon
9545163b1c arm64: dts: rockchip: Add rk3588 GPU node
Add Mali GPU Node to the RK3588 SoC DT including GPU clock
operating points

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 6fca4edb93d335f29f81e484936f38a5eed6a9b1 ]

(cherry picked from commit 3cd15354ea0c8668812bc0b3a4136606c10803e9)
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-06-14 17:11:05 +08:00
Quentin Schulz
f087f7fd27 rockchip: px30/rk3326: migrate to OF_UPSTREAM
Migrate PX30/RK3326 boards that exists in Linux v6.8 to use OF_UPSTREAM.

firefly-px30 is not migrated to OF_UPSTREAM because there's no Device
Tree in the Linux kernel.

Differences between U-Boot's Odroid-Go2 and Linux's are now moved to the
-u-boot.dtsi, though I have a gut feeling that the existing cru
overrides aren't necessary (anymore?).

The U-Boot GPIO led-0 is on GPIO0_C1 but such is the pin of PWM3 which
is used for Linux's PWM led-2 so keep Linux's.

I also doubt vcc_cam is actually used, though the Odroid-Go2 Black
Edition uses this dcdc regulator for WiFi, so let's just move it to the
-u-boot.dtsi to play it safe.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:10:42 +08:00
Quentin Schulz
c1fe766046 rockchip: evb-px30: make UART5 the debug UART
In the Device Tree, UART5 is the system UART, but in the defconfig it
currently is UART2. Let's sync the two by making the defconfig use UART5
as well.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:10:42 +08:00
Quentin Schulz
caa9456d61 rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB
In order to be able to properly mux UART on PX30 EVB, the pinmux needs
to be done at runtime, so let's not remove the pinctrl nodes from the
SPL DTB.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:10:42 +08:00
Quentin Schulz
7fca4d8914 rockchip: px30: make UART pinmux accessible to TPL/SPL DTB
This adds the default pinmux for UART2 and UART5 to the TPL/SPL DTB (if
not removed through the CONFIG_OF_SPL_REMOVE_PROPS symbol) as those two
controllers are always made available to all boards.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:10:42 +08:00
Quentin Schulz
94537d2f33 rockchip: px30-core-*: Use common bss and stack addresses
U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:10:42 +08:00
Quentin Schulz
86307b1b04 rockchip: odroid-go2: Use common bss and stack addresses
U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:10:42 +08:00
Quentin Schulz
742c6eb36a rockchip: firefly-px30: Use common bss and stack addresses
U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:10:42 +08:00
Quentin Schulz
e6b1080d1e rockchip: evb-px30: Use common bss and stack addresses
U-Boot proper pre-reloc is currently running out of memory on PX30
Ringneck and it is thus impossible to boot into U-Boot CLI. It is
assumed the same problem can be seen on other PX30 boards though I
cannot guarantee it since I don't have access to them.

Fix this by migrating to the common bss and stack addresses for PX30,
which drastically increases the size of the pre-reloc allocation pool (8
times bigger now). The memory layout in SPL and U-Boot proper now
match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-06-14 17:10:42 +08:00
Love Kumar
0786dd573d test/py: net_boot: Add test cases for net boot
Add tests for booting image using tftpboot/pxe boot commands, tftpboot
boot case loads the FIT image into DDR and boots using bootm command
whereas pxe boot cases downloads the pxe configuration file from the
TFTP server and interprets it to boot the images mentioned in the pxe
configurations file.
This test relies on boardenv_* containing configuration values including
the parameter 'pattern'. tftpboot/pxe boot cases boots the Linux till the
boot log pattern value is matched. For example, if the parameter
'pattern' is defined as 'login:', it will boot till login prompt.

Signed-off-by: Love Kumar <love.kumar@amd.com>
Tested-by: Tom Rini <trini@konsulko.com>
2024-06-13 16:31:24 -06:00
Love Kumar
a57973ab47 test/py: Add support to enable check for bad pattern
Executing a u-boot command may raise an error or extra bad pattern,
beyond the default bad patterns. Providing a way to enable the console
output error check in test.

For example, description for OS boot test:
import re
check_type = 'kernel_boot_error'
check_pattern = re.compile('ERROR -2: can't get kernel image!')
with u_boot_console.enable_check(check_type, check_pattern):
    u_boot_console.run_command('<boot command>')

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-06-13 16:31:20 -06:00
Mattijs Korpershoek
065ed551e3 cmd: bcb: Fix bcb compilation when CONFIG_CMD_BCB=n
commit dfeb4f0d7935 ("cmd: bcb: extend BCB C API to allow read/write the fields")
introduced the bcb_get() function.

When CONFIG_CMD_BCB=n, that function is stubbed.
The stubbed function has a wrong prototype: value_size arg is missing.

Add the missing argument to fix build when CONFIG_CMD_BCB=n.

Fixes: dfeb4f0d7935 ("cmd: bcb: extend BCB C API to allow read/write the fields")
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Dmitrii Merkurev <dimorinny@google.com>
Reviewed-by: Julien Masson <jmasson@baylibre.com>
2024-06-13 16:30:48 -06:00
Dmitry Gerasimov
822911d574 imxtract: add support for zstd-compressed images
Allow extraction of zstd-compressed images from FIT using imxtract
command. This is especially useful when one has to load an image via
some interface (e.g. SPI) rather that just to the memory.

Signed-off-by: Dmitry Gerasimov <di.gerasimov@gmail.com>
2024-06-13 16:30:47 -06:00
Yasuharu Shibata
b993bd65ec bcmgenet: fix Rx buffer corruption caused by lack of cache flush
When bcmgenet complete to write Rx buffer with the DMA,
some U-Boot commands write data to the buffer directly.
Those write data will become dirty in CPU cache.
After this driver calls free_pkt to the buffer,
the buffer is assigned as the future Rx buffer.
At some point, if bcmgenet writes to a buffer with DMA
and CPU cache flushes dirty data to the buffer,
the buffer is corrupted.

This patch calls flush_dcache_range in free_pkt
to immediately flush the data written by U-Boot command
and prevent data corruption.

This issue can be reproduced using wget on Raspberry Pi4.
If wget receives data larger than
RX_BUF_LENGTH * RX_DESCS = 2048 * 256 bytes,
it will timeout due to data corruption.
In addition, if LOG_DEBUG is enabled in net/tcp.c,
the following error log is output.

TCP RX TCP xSum Error

Signed-off-by: Yasuharu Shibata <yasuharu.shibata@gmail.com>
2024-06-13 16:30:46 -06:00
Jonathan Humphreys
5053784e62 configs: j784s4: Enable OSPI NOR boot
Set necessary configs to enable the j784s4 device to boot from OSPI NOR
flash.

Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
2024-06-13 16:30:44 -06:00
Vignesh Raghavendra
081b97c3b3 spl: Kconfig: ARCH_K3: Set default SPL_STACK_R_MALLOC_SIMPLE_LEN for R5 build
All ARCH_K3 platforms need about of 2MB of malloc space post
reallocation. Since, this space is allocated from SDRAM, provide a
generous 2MB space by default.

Platforms requiring more than 2MB can override in defconfig as needed.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2024-06-13 16:29:26 -06:00
Neha Malcom Francis
279567ad68 arm: dts: k3-*-binman: Make default DM file optional
The default DM firmware path is non-optional as of now. Make it
optional so that users that choose to provide DM via TI_DM argument
instead of BINMAN_INDIRS can do so without build errors.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2024-06-13 16:29:22 -06:00
Neha Malcom Francis
4c3a9113d9 env: ti: k3_dfu: Drup mmcpart for rootfs
According to [0], raw access to mmc should not have mmcpart in the
entry. This was fixed in k3_dfu_combined.env but k3_dfu.env had been
overlooked.

[0] doc/usage/dfu.rst

Fixes: 53b406369e9d ("DFU: Check the number of arguments and argument string strictly")
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2024-06-13 16:29:20 -06:00
Neha Malcom Francis
939f17c8a9 arm: dts: k3-j721s2-r5: Change GTC clock parent
MAIN_PLL0 has a flag set in DM (Device Manager) that removes its
capability to re-initialise clock frequencies. A72 CPU clock (GTC) and
RGMII has MAIN_PLL3 as their parent which does not have this flag. While
RGMII needs re-initialization to default frequency to be able to get
250MHz with its divider, GTC can not get its required 200MHz with its
dividers. Thus move GTC clock parent on J721S2 from MAIN_PLL3_HSDIV1 to
MAIN_PLL0_HSDIV6. This was already done on CPTS node in kernel which was
similarly affected (linked).

Link: https://lore.kernel.org/all/20230605110443.84568-1-n-francis@ti.com/
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2024-06-13 16:29:17 -06:00
Marek Vasut
6610375959 net: phy: Replace PHY_ANEG_TIMEOUT with Kconfig symbol
Switch PHY_ANEG_TIMEOUT to CONFIG_PHY_ANEG_TIMEOUT Kconfig symbol.
This removes one more configuration headers option finalizes its
Kconfig symbol conversion. No functional change expected.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-06-13 16:27:07 -06:00
Marek Vasut
4031a4299c net: phy: Turn default auto-negotiation timeout into Kconfig symbol
Let users configure default auto-negotiation timeout via Kconfig
instead of specifying it in board configuration headers. This is
the first step toward converting this to Kconfig fully, so far the
legacy PHY_ANEG_TIMEOUT in configuration headers takes precedence.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-06-13 16:27:06 -06:00
Tom Rini
3db3a6ba7b Merge patch series "Enable OSPI boot for j721s2"
Manorit Chawdhry <m-chawdhry@ti.com> says:

The series enables ospi boot for j721s2.

Test logs: https://gist.github.com/manorit2001/6bb91885c608e3a8cb0267ab2c614781
2024-06-13 08:20:30 -06:00
Manorit Chawdhry
1c86db01fb configs: j721s2_evm_*_defconfig: Enable OSPI configs
Enable OSPI related configs to boot using OSPI

Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-06-12 18:40:37 -06:00
Manorit Chawdhry
595dbb44aa arch: arm: dts: k3-j721s2-*-u-boot.dtsi: Enable the ospi0 node
Enable ospi0 node for all boot stages

Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-06-12 18:40:37 -06:00
Manorit Chawdhry
512863ecfe arch: arm: dts: k3-j721s2-r5: Override ospi and fss for 32-bit mode
R5 being a 32-bit processor can't understand the 64-bit mapping being
done in ospi node. Override the ospi node for 32-bit register ranges and
the fss node ( the parent node of ospi ) to map the ranges for the
updated child node correctly.

Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-06-12 18:40:37 -06:00
Pratyush Yadav
11d5655919 mtd: spi-nor-core: Do not start or end writes at odd address in DTR mode
On DTR capable flashes like Micron Xcella the writes cannot start or end
at an odd address in DTR mode. Extra 0xff bytes need to be prepended or
appended respectively to make sure both the start and end addresses are
even.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Jonathan Humphreys <j-humphreys@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-06-12 18:40:37 -06:00
Tom Rini
9cf83a7da9 Pull request efi-next-20240611
UEFI:
 
 * Allow specifying a device-tree in an EFI load option
   using the efidebug or eficonfig command.
 * Let the EFI boot manager fall back to an OS provided device-tree
   if no device-tree is specified.
 -----BEGIN PGP SIGNATURE-----
 
 iQJWBAABCABAFiEEK7wKXt3/btL6/yA+hO4vgnE3U0sFAmZoOXUiHGhlaW5yaWNo
 LnNjaHVjaGFyZHRAY2Fub25pY2FsLmNvbQAKCRCE7i+CcTdTS36HEACegzro+P2f
 XZbdiRi0zN+ef5UkUVm/LECwBWXo0p9R5L3XWsRtxz8nqzG5JgB4lzDr0X3cRAVr
 uUeg6xf5LSXCbme/Ct68bi27F54Z0OQDmVlvPC/zUQ6CUDPg+0HFlHiBgKGvkAy+
 0HZY57OhXbviyuZ8JND/zL5GBGnyVGjyoghS0OvtSeWZ+6JIHYrMGH9fc1jtdS4+
 jleIkKE4NKIJPOPQVpCr84SgtbsfFeaOtsAM6u5Asd8FkmKLjcgNpKw5Kj03vJwP
 javMY/hG7LkAxHLEfDOe1A3z8AKqN+zrHZ0Rj7Xy+TdwEmh6IgsPkorPCjWa5g0W
 Cp7pjf2Bq/dAZLhHCMPFBQ/aSv9t3b+LSdrGYJUffwmjhcJ/6+J+2ioD50cJc31E
 Ov85HF7FpB9s82+3LL9QuFkQIdDdseNPCPUdEesA1GJjZUa8QrrrmmeTDuZZAmXm
 HpAy3/hw1lTYG/yPSavQdr0bZNTcersvpIqchI5b/SXfAH+riSSuGGobtaYE61su
 2esMKTMma1/aO2X3i7QCTntG4fKd/7Wfbf3lcjIJ3nuWlty+AvXZiD1nHM48d2P4
 U3/Wbsls60mlAG/P15/eC8jxhkanrbSXNwGOjJMbh+OmwUukhvYg+35t5qZkCwuW
 OHIFOWhFuIs+tsEUoOllZldDgmWB9hpjxg==
 =D5PO
 -----END PGP SIGNATURE-----

Merge tag 'efi-next-20240611' of https://source.denx.de/u-boot/custodians/u-boot-efi into next

Pull request efi-next-20240611

UEFI:

* Allow specifying a device-tree in an EFI load option
  using the efidebug or eficonfig command.
* Let the EFI boot manager fall back to an OS provided device-tree
  if no device-tree is specified.
2024-06-11 07:42:55 -06:00
Heinrich Schuchardt
535321c2ea efi_loader: rename struct efi_initrd_dp to efi_lo_dp_prefix
As we now also store device-tree device-paths in load options rename
struct efi_initrd_dp to efi_lo_dp_prefix.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-06-10 11:43:37 +02:00
Heinrich Schuchardt
e91b68fd6b efi_loader: load distro dtb in bootmgr
If no device-tree is specified, try to load a device-tree from the boot
device use the $fdtfile concatenated to either of the paths '/dtb/', '/',
'/dtb/current/'.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-06-10 11:43:37 +02:00
Heinrich Schuchardt
8deb5d855b efi_loader: export efi_load_image_from_path
We can reuse this function to load the device-tree.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-06-10 11:43:36 +02:00
Heinrich Schuchardt
b34528ebad efi_loader: return binary from efi_dp_from_lo()
For finding distro supplied device-trees we need to know from which device
we are booting. This can be identified via the device-path of the binary.

Up to now efi_dp_from_lo() only could return the initrd or fdt device-path.
Allow returning the binary device-path, too.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-06-10 11:43:36 +02:00
Heinrich Schuchardt
c946385950 efi_loader: move distro_efi_get_fdt_name()
Move distro_efi_get_fdt_name() to a separate C module
and rename it to efi_get_distro_fdt_name().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-06-10 11:43:36 +02:00
Heinrich Schuchardt
39bac24a48 efi_loader: load device-tree specified in boot option
We allow to specify the triple of binary, initrd, and device-tree in boot
options.

Add the code to actually load the specified device-tree.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-06-10 11:43:36 +02:00
Heinrich Schuchardt
d9f7f42451 cmd: efidebug: add support for setting fdt
We already support creating a load option where the device-path
field contains the concatenation of the binary device-path and
optionally the device path of the initrd which we expose via the
EFI_LOAD_FILE2_PROTOCOL.

Allow to append another device-path pointing to the device-tree
identified by the device-tree GUID.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-06-10 11:43:36 +02:00